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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 883 records · Page 49
All sourcesNASA NTRSDOE OSTI
DOE OSTI2013

A Latency Tolerant Runtime System for Mass Market Computer Systems

Grappa is a latency tolerant runtime system for mass market computer systems comprised of multiple nodes having x86 multicore processors and infiniband interconnect. Grappa is designed to enable in-memory irregular applications written in the C++ programming language to scale up on multiprocessor systems. Grappa addresses the load balance, communication, and synchronization challenges posed by running applications that do not partition evenly across large systems. Two mechanisms are essential to its success: fast task switching and message aggregation. Fast task switching enables processors to tolerate communication and synchronization delays; aggregation sustains high bandwidth on low injection rate networks.

Source record↗
DOE OSTI2017

Method, system, and computer-readable medium for determining performance characteristics of an object undergoing one or more arbitrary aging conditions

A method, system, and computer-readable medium are described for characterizing performance loss of an object undergoing an arbitrary aging condition. Baseline aging data may be collected from the object for at least one known baseline aging condition over time, determining baseline multiple sigmoid model parameters from the baseline data, and performance loss of the object may be determined over time through multiple sigmoid model parameters associated with the object undergoing the arbitrary aging condition using a differential deviation-from-baseline approach from the baseline multiple sigmoid model parameters. The system may include an object, monitoring hardware configured to sample performance characteristics of the object, and a processor coupled to the monitoring hardware. The processor is configured to determine performance loss for the arbitrary aging condition from a comparison of the performance characteristics of the object deviating from baseline performance characteristics associated with a baseline aging condition.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Computer systems and methods for the query and visualization multidimensional databases

A method of generating a data visualization is performed at a computer having a display, one or more processors, and memory. The memory stores one or more programs for execution by the one or more processors. The process receives user specification of a plurality of characteristics of a data visualization. The data visualization is based on data from a multidimensional database. The characteristics specify at least x-position and y-position of data marks corresponding to tuples of data retrieved from the database. The process generates a data visualization according to the specified plurality of characteristics. The data visualization has an x-axis defined based on data for one or more first fields from the database that specify x-position of the data marks and the data visualization has a y-axis defined based on data for one or more second fields from the database that specify y-position of the data marks.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2016

Overcoming the Power Wall by Exploiting Application Inexactness and Emerging COTS Architectural Features

Abstract—Energy and power consumption are major limitations to continued scaling of computing systems. Inexactness where the quality of the solution can be traded for energy savings has been proposed as a counterintuitive approach to overcoming those limitation. However, in the past, inexactness has been necessitated the need for highly customized or specialized hardware. In order to move away from customization, in earlier work [4], it was shown that by interpreting precision in the computation to be the parameter to trade to achieve inexactness, weather prediction and page rank could both benefit in terms of yielding energy savings through reduced precision, while preserving the quality of the application. However, this required representations of numbers that were not readily available on commercial off-the-shelf (COTS) processors. In this paper, we provide opportunities for extending the the notion of trading precision for energy savings into the world COTS. We provide a model and analyze the opportunities and behavior of all three IEEE compliant precision values available on COTS processors: (i) double (ii) single, and (iii) half. Through measurements, we show through a limit study energy savings in going from double to half precision can potentially exceed a factor of four, largely due to memory and cache effects.

Fagan, Mike↗
DOE OSTI2017

Method and apparatus for managing access to a memory

A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operational memory layout reduces an amount of energy consumed by the processor to perform the computing job.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Trip optimization system and method for a train

A system for operating a train having one or more locomotive consists with each locomotive consist comprising one or more locomotives, the system including a locator element to determine a location of the train, a track characterization element to provide information about a track, a sensor for measuring an operating condition of the locomotive consist, a processor operable to receive information from the locator element, the track characterizing element, and the sensor, and an algorithm embodied within the processor having access to the information to create a trip plan that optimizes performance of the locomotive consist in accordance with one or more operational criteria for the train.

42 ENGINEERING↗
DOE OSTI2017

System and method of detecting cavitation in pumps

A system and method for detecting cavitation in pumps for fixed and variable supply frequency applications is disclosed. The system includes a controller having a processor programmed to repeatedly receive real-time operating current data from a motor driving a pump, generate a current frequency spectrum from the current data, and analyze current data within a pair of signature frequency bands of the current frequency spectrum. The processor is further programmed to repeatedly determine fault signatures as a function of the current data within the pair of signature frequency bands, repeatedly determine fault indices based on the fault signatures and a dynamic reference signature, compare the fault indices to a reference index, and identify a cavitation condition in a pump based on a comparison between the reference index and a current fault index.

42 ENGINEERING↗
DOE OSTI2017

Smoke detection

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDA training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.

47 OTHER INSTRUMENTATION↗
DOE OSTI2017

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2017

Bias by default? A means for a priori interface measurement

Systems have biases. Their interfaces naturally guide a user toward specific patterns of action. For example, modern word-processors and spreadsheets are both capable of taking word wrapping, checking spelling, storing tables, and calculating formulas. You could write a paper in a spreadsheet or could do simple business modeling in a word-processor. However, their interfaces naturally communicate which function they are designed for. Visual analytic interfaces also have biases. In this paper, we outline why simple Markov models are a plausible tool for investigating that bias and how they might be applied. We also discuss some anticipated difficulties in such modeling and touch briefly on what some Markov model extensions might provide.

Cottam, Joseph A.↗
DOE OSTI2018

Load power device, system and method of load control and management employing load identification

A load power device includes a power input, at least one power output for at least one load, a plurality of sensors structured to sense voltage and current at the at least one power output, and a processor. The processor provides: (a) load identification based upon the sensed voltage and current, and (b) load control and management based upon the load identification.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2018

Performing stencil computations

A method and apparatus for performing stencil computations efficiently are disclosed. In one embodiment, a processor receives an offset, and in response, retrieves a value from a memory via a single instruction, where the retrieving comprises: identifying, based on the offset, one of a plurality of registers of the processor; loading an address stored in the identified register; and retrieving from the memory the value at the address.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Modular chemiresistive sensor

The present invention relates to a modular chemiresistive sensor. In particular, a modular chemiresistive sensor for hypergolic fuel and oxidizer leak detection, carbon dioxide monitoring and detection of disease biomarkers. The sensor preferably has two gold or platinum electrodes mounted on a silicon substrate where the electrodes are connected to a power source and are separated by a gap of 0.5 to 4.0 .mu.M. A polymer nanowire or carbon nanotube spans the gap between the electrodes and connects the electrodes electrically. The electrodes are further connected to a circuit board having a processor and data storage, where the processor can measure current and voltage values between the electrodes and compare the current and voltage values with current and voltage values stored in the data storage and assigned to particular concentrations of a pre-determined substance such as those listed above or a variety of other substances.

47 OTHER INSTRUMENTATION↗
DOE OSTI2015

Java Source Code Analysis for API Migration to Embedded Systems

Embedded systems form an integral part of our technological infrastructure and oftentimes play a complex and critical role within larger systems. From the perspective of reliability, security, and safety, strong arguments can be made favoring the use of Java over C in such systems. In part, this argument is based on the assumption that suitable subsets of Java’s APIs and extension libraries are available to embedded software developers. In practice, a number of Java-based embedded processors do not support the full features of the JVM. For such processors, source code migration is a mechanism by which key abstractions offered by APIs and extension libraries can made available to embedded software developers. The analysis required for Java source code-level library migration is based on the ability to correctly resolve element references to their corresponding element declarations. A key challenge in this setting is how to perform analysis for incomplete source-code bases (e.g., subsets of libraries) from which types and packages have been omitted. This article formalizes an approach that can be used to extend code bases targeted for migration in such a manner that the threats associated the analysis of incomplete code bases are eliminated.

Winter, Victor↗
DOE OSTI2018

System and method for analyzing oscillatory stability in electrical power transmission systems

A computer-based method for contingency analysis of oscillatory stability in an electrical power transmission system is provided. The method uses at least one processor. The method includes receiving, by the at least one processor, a plurality of component inputs from a plurality of system components within the electrical power transmission system. The method also includes generating a nominal matrix for the electrical power transmission system. The nominal matrix includes a set of equations at least partially modeling the electrical power transmission system. The method further includes calculating eigenvalues and eigenvectors of the nominal matrix. The method also includes identifying a contingency representing a postulated disturbance of the electrical power transmission system. The method further includes estimating a contingency eigenvalue for the contingency using the eigenvalues and eigenvectors of the nominal matrix.

Baone, Chaitanya Ashok↗
DOE OSTI2018

ANALYSIS OF COMMUNICATION PERFORMANCE DEGRADATION OF THE RADIATION TRANSPORT CODE PIDOTS ON HIGH-UTILIZATION, MULTI-USER HPC SYSTEMS

The PIDOTS radiation transport code implements a spatially decomposed Integral Transport Matrix Method (ITMM) solver, which is intended to fully utilize the capabilities of modern, massively parallel high-performance computing (HPC) systems. While the code shows promising results, there was also an unexpected loss of parallel efficiency on the test systems as the number of participating processors grew and the parallelization grain size got finer. We seek to identify and characterize the communication-latency based effects that contribute to this slowdown. Through the creation of a high-level, parameterized representation of the workload of the code, the communication methodology was identified as the likely reason. From there, low-level, InfiniBand communication performance data measured on the Falcon HPC at Idaho National Laboratory (INL) was used to produce a discrete-event model of the communication scheme. The data, as well as the model, show that infrequent, large spikes in send/receive latency drive an unexpectedly substantial increase in projected runtime of a code. Furthermore, these effects are more pronounced under the high-utilization, scattered-workload environment of Falcon. Based on results from the model, it can be shown that a high-communication volume, small message-size regime can easily lead to slowdowns of ~5-10x, when compared to ideal results, as the processor count increases.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Method for instruction sequence execution analysis and visualization

Various technologies pertaining to computer-executable instruction sequence forensics are described herein. In a general embodiment, an application development framework supports a function library that includes a plurality of recording functions. Calls to these functions are inserted into source code or bytecode of the computer-executable instruction sequence. The source code is then compiled, resulting in formation of instrumented machine code of the computer-executable instruction sequence. Alternately, the runtime environment interprets instrumented bytecode for the instruction sequence. A processor executes the machine code, and the called functions cause the processor to generate forensic data pertaining to portions of the computer-executable instruction sequence that correspond to locations in the source code where the calls were inserted. An execution instance of the computer-executable instruction sequence is visualized based upon the forensic data.

Sundermier, Amy↗
DOE OSTI2018

Real time voltage regulation through gather and broadcast techniques

An example device includes a processor configured to receive a plurality of voltage measurements corresponding to nodes in a distribution network, and determine, for each respective node: a value of a first coefficient, based on a previous value of the first coefficient, a minimum voltage value for the node, and a voltage measurement that corresponds to the node, and a value of a second coefficient based on a previous value of the second coefficient, a maximum voltage value for the node, and the voltage measurement. The processor of the example device is also configured to cause an inverter-interfaced energy resource connected to the distribution network to modify its output power based on the value of the first coefficient for each node and the value of the second coefficient for each node.

42 ENGINEERING↗