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At least 883 records · Page 49

Performance of concatenated Reed-Solomon/Viterbi channel coding

The concatenated Reed-Solomon (RS)/Viterbi coding system is reviewed. The performance of the system is analyzed and results are derived with a new simple approach. A functional model for the input RS symbol error probability is presented. Based on this new functional model, we compute the performance of a concatenated system in terms of RS word error probability, output RS symbol error probability, bit error probability due to decoding failure, and bit error probability due to decoding error. Finally we analyze the effects of the noisy carrier reference and the slow fading on the system performance.

Divsalar, D.↗

The Reed-Solomon encoders: Conventional versus Berlekamp's architecture

Concatenated coding was adopted for interplanetary space missions. Concatenated coding was employed with a convolutional inner code and a Reed-Solomon (RS) outer code for spacecraft telemetry. Conventional RS encoders are compared with those that incorporate two architectural features which approximately halve the number of multiplications of a set of fixed arguments by any RS codeword symbol. The fixed arguments and the RS symbols are taken from a nonbinary finite field. Each set of multiplications is bit-serially performed and completed during one (bit-serial) symbol shift. All firmware employed by conventional RS encoders is eliminated.

Perlman, M.↗

The Earth Resources Laboratory Applications Software (ELAS) in university research and education: An operator oriented geobased information system

Created for analyzing and processing digital data such as that collected by multispectral scanners or digitized from maps, ELAS is designed for ease of user operation and includes its own FORTRAN operating monitor and an expandable set of application modules which are FORTRAN overlays. On those machines that do not support FORTRAN overlaying, the modules exist as subprograms. The subsystem can be implemented on most 16-bit or 32-bit machines and is capable of, but not limited to, operating on low-cost minicomputer systems. The recommended hardware configuration for ELAS and a representative listing of some operating and application modules are presented.

Coker, B. L.↗

Information content of data from the LANDSAT-4 Thematic Mapper (TM) and Multispectral Scanner (MSS)

Software was constructed to reformat data to band interlevel format and analysis software was developed in an effort to quantify the increased information content (statistical variability within a data set) of thematic mapper data as compared to that from the LANDSAT 4 multispectral band scanner. Computer runs were carried out for several subareas from a data set acquired simultaneously by TM and MSS over a test area in northeast Arkansas, one of the most agriculturally diverse sea areas in the country. The 6 visible-near IR channels of the TM provide more information than the 4 channels of the MSS. A rough estimate of 20 bits per pixel for TM, and 10 bits per pixel for the MSS was computed for these subareas. These numbers are to be revised downward when allowance is made for noise in the data.

Price, J. C.↗

Distributed multiport memory architecture

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Kohl, W. H.↗

Implementation of the DAST ARW II control laws using an 8086 microprocessor and an 8087 floating-point coprocessor

A 5 MHZ single-board microprocessor system which incorporates an 8086 CPU and an 8087 Numeric Data Processor is used to implement the control laws for the NASA Drones for Aerodynamic and Structural Testing, Aeroelastic Research Wing II. The control laws program was executed in 7.02 msec, with initialization consuming 2.65 msec and the control law loop 4.38 msec. The software emulator execution times for these two tasks were 36.67 and 61.18, respectively, for a total of 97.68 msec. The space, weight and cost reductions achieved in the present, aircraft control application of this combination of a 16-bit microprocessor with an 80-bit floating point coprocessor may be obtainable in other real time control applications.

Kelly, G. L.↗

The dependence of single event upset on proton energy /15-590 MeV/

Low earth orbit satellite and Jupiter orbiter probe semiconductor devices may incur soft errors or single event upsets, manifested as bit flips, during exposure to such nuclear particles or heavy ions as trapped protons with energies ranging up to 1000 MeV. Experimental data is given on the average proton fluence needed to cause a bit flip as a function of proton energy for isoplanar bipolar TTL RAMs. Error dependence data shape and threshold energy can be related to the existing body of theoretical data on energy deposition following proton nuclear reactions. Experimental data also show that the relative cross sectional amplitude for functionally identical devices can be related to the device's power consumption.

Nichols, D. K.↗

New two-dimensional photon camera

A photon-sensitive camera, applicable to speckle imaging of astronomical sources, high-resolution spectroscopy of faint galaxies in a crossed-dispersion spectrograph, or narrow-band direct imaging of galaxies, is presented. The camera is shown to supply 8-bit by 8-bit photon positions (256 x 256 pixels) for as many as 10 to the 6th photons/sec with a maximum linear resolution of approximately 10 microns. The sequence of photon positions is recorded digitally with a VHS-format video tape recorder or formed into an immediate image via a microcomputer. The four basic elements of the camera are described in detail: a high-gain image intensifier with fast-decay output phosphor, a glass-prism optical-beam splitter, a set of Gray-coded masks, and a photomultiplier tube for each mask. The characteristics of the camera are compared to those of other photon cameras.

Papaliolios, C.↗

A study on airborne integrated display system and human information processing

The cognitive behavior of pilots was examined in an experiment involving mock ups of an eight display electronic attitude direction indicator for an airborne integrated display. Displays were presented in digital, analog digital, and analog format to experienced pilots. Two tests were run, one involving the speed of memorization in a single exposure and the other comprising two five second exposures spaced 30 sec apart. Errors increased with the speed of memorization. Generally, the analog information was assimilated faster than the digital data, with regard to the response speed. Information processing was quantified as 25 bits for the first five second exposure and 15 bits during the second.

Mizumoto, K.↗

The 30-GHz monolithic receive module

Key requirements for a 30 GHz GaAs monolithic receive module for spaceborne communication antenna feed array applications include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five-bit phase shifter, and a maximum power consumption of 250 mW. The RF designs for each of the four submodules (low noise amplifier, some gain control, phase shifter, and RF to IF sub-module) are presented. Except for the phase shifter, high frequency, low noise FETs with sub-half micron gate lengths are employed in the submodules. For the gain control, a two stage dual gate FET amplifier is used. The phase shifter is of the passive switched line type and consists of 5-bits. It uses relatively large gate width FETs (with zero drain to source bias) as the switching elements. A 20 GHz local oscillator buffer amplifier, a FET compatible balanced mixer, and a 5-8 GHz IF amplifier constitute the RF/IF sub-module. Phase shifter fabrication using ion implantation and a self-aligned gate technique is described. Preliminary RF results obtained on such phase shifters are included.

Sokolov, V.↗

Microprocessor based implementation of attitude and shape control of large space structures

The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.

Reddy, A. S. S. R.↗

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.

Costello, D. J., Jr.↗

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗

Quick Look Analysis of TM Data of the Washington, District of Columbia Area

A fixed factor analysis-of-variance (ANOVA) approach was used to quantify the impact of each TM sensor characteristic (spectral, spatial, and radiometric resolutions) on classification accuracy. All assessments were made relative to MSS sensor characteristics, and the impact of each characteristic was assessed individually, and in all possible combinations. Thematic Mapper data acquired over the Washington, D.C. area on November 2, 1982 were utilized to conduct the experiment. The following results were obtained: the reduction of quantization level from eight bits to six bits caused a decrease in overall accuracy (7%); the use of only three bands (TM 2, 3 and 4) covering the isible and near infrared portion of the spectrum caused a decrease in overall accuracy (7%); and the decrease in spatial resolution resulted in an increase in overall accuracy (4%). Results indicate that the increased radiometric and spectral resolution of the TM instrument do provide increased information content. The result of the spatial resolution degradation is somewhat misleading, in that the result is more a function of spatial resolution.

Williams, D. L.↗

Comparison of the information content of data from the LANDSAT-4 Thematic Mapper and the Multispectral Scanner

Simultaneous data acquisition by the LANDSAT-4 Thematic Mapper (TM) and the multispectral scanner (MSS) permits the comparison of the two types of image data with respect to engineering performance and data applications. The information contained in five matching scenes in agricultural areas is evaluated for the visible and near-IR channels, leading to the conclusion that the TM provides a significant advance in information gathering capability as expressed in terms of either bits per pixel or bits per unit area.

Price, J. C.↗

Research in the design of high-performance reconfigurable systems

An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.

Slotnick, D. L.↗

A Ka-band GaAs monolithic phase shifter

The design and performance of a GaAs monolithic 180-degree one-bit switched line phase shifter test circuit for Ka-band operation is presented. A self-aligned gate (SAG) fabrication technique is also described that reduces resistive parasitics in the switching FET's. Over the 27.5-30 GHz band, typical measured differential insertion phase is within 10-20 deg of the ideal time delay characteristic. Over the same band, the insertion loss for the SAG phase shifter is about 2.5-3 dB per bit. The SAG fabrication technique holds promise in reducing phase shifter insertion loss to about 1.5 dB/bit for 30-GHz operation.

Sokolov, V.↗

Single event upset (SEU) of semiconductor devices - A summary of JPL test data

The data summarized describe single event upset (bit-flips) for 60 device types having data storage elements. The data are from 15 acceleration tests with both protons and heavier ions. Tables are included summarizing the upset threshold data and listing the devices tested for heavy ion induced bit-flip and the devices tested with protons. With regard to the proton data, it is noted that the data are often limited to one proton energy, since the tests were usually motivated by the engineering requirement of comparing similar candidate devices for a system. It is noted that many of the devices exhibited no upset for the given test conditions (the maximum fluence and the maximum proton energy Ep are given for these cases). It is believed, however, that some possibility of upset usually exists because there is a slight chance that the recoil atom may receive up to 10 to 20 MeV of recoil energy (with more energy at higher Ep).

Nichols, D. K.↗