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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1966

Subroutine allows easy computation in extended precision arithmetic

Subroutine called NPREC allows relatively simple computation of very large numbers or very small fractions with extreme accuracy. This subroutine handles numbers that consist of 35 binary bits /1 word/ for the exponent and 70 bits /2 words/ for the fraction.

Berggren, R. L.↗
NASA NTRS1972

Significance arithmetic experimental package (SIGPAC)

Method for use by computing facility to determine accuracy of computer calculations is presented. Primary goals of error analysis program are described. Program is designed for both FORTRAN 4 and ASSEMBLER for use with IBM 360 computer.

Cole, I.↗
NASA NTRS1977

Fast arithmetic in MacLISP

MacLISP provides a compiler which produces numerical code competitive in speed with some FORTRAN implementations and yet compatible with the rest of the MacLISP system. All numerical programs can be run under the MacLISP interpreter. Additional declarations to the compiler specify type information which allows the generation of optimized numerical code which generally does not require the garbage collection of temporary numerical results. Array accesses are almost as fast as in FORTRAN, and permit the use of dynamically allocated arrays of varying dimensions. The implementation decisions regarding user interface, data representations, and interfacing conventions are discussed which allow the generation of fast numerical LISP code.

Steele, G. L., Jr.↗
NASA NTRS1975

The realization of arithmetic processors for delta modulation encoded signals

The design and realization of digital devices which add or multiply delta modulation (DM) encoded signals are presented. These systems operate directly on the DM bit stream. It is shown that the devices can be constructed using standard digital hardware and that the hardware complexity needed to add or multiply the two DM encoded signals is equivalent to that needed for pulse code modulation (PCM) signals. Experimental results are presented showing the operation of these systems. The results obtained by adding or multiplying DM encoded signals are compared with those obtained using PCM encoded signals on the basis of signal-to-noise ratio (SNR). A spectral-analysis technique applicable to a DM encoded signal is developed to obtain SNR curves.

Locicero, J. L.↗
NASA NTRS1978

FPLA mechanization of arithmetic elements to produce A + B or to pass A only

A 4-bit and a 3-bit adder are described which can be implemented under special hardware restrictions. The chip to be used is field-programmable logic array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an enable function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 74S182.

Wallis, D. E.↗
NASA NTRS1986

Derivatives of the Arithmetic-Geometric Mean

Developed for theoretical studies of lightning requiring estimates of electric fields in clouds, the technique is expected to reduce computation time and improve accuracy.

Taton, F. B.↗
NASA NTRS1986

Workspace Program for Complex-Number Arithmetic

COMPLEX is workspace program designed to empower APL with complexnumber capabilities. Complex-variable methods provide analytical tools invaluable for applications in mathematics, science, and engineering. COMPLEX written in APL.

Patrick, M. C.↗
NASA NTRS1990

Application specific serial arithmetic arrays

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

Winters, K.↗
NASA NTRS2005

Reconfigurable data path processor

A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

Donohoe, Gregory↗
NASA NTRS2008

Efficient Probabilistic Diagnostics for Electrical Power Systems

We consider in this work the probabilistic approach to model-based diagnosis when applied to electrical power systems (EPSs). Our probabilistic approach is formally well-founded, as it based on Bayesian networks and arithmetic circuits. We investigate the diagnostic task known as fault isolation, and pay special attention to meeting two of the main challenges . model development and real-time reasoning . often associated with real-world application of model-based diagnosis technologies. To address the challenge of model development, we develop a systematic approach to representing electrical power systems as Bayesian networks, supported by an easy-to-use speci.cation language. To address the real-time reasoning challenge, we compile Bayesian networks into arithmetic circuits. Arithmetic circuit evaluation supports real-time diagnosis by being predictable and fast. In essence, we introduce a high-level EPS speci.cation language from which Bayesian networks that can diagnose multiple simultaneous failures are auto-generated, and we illustrate the feasibility of using arithmetic circuits, compiled from Bayesian networks, for real-time diagnosis on real-world EPSs of interest to NASA. The experimental system is a real-world EPS, namely the Advanced Diagnostic and Prognostic Testbed (ADAPT) located at the NASA Ames Research Center. In experiments with the ADAPT Bayesian network, which currently contains 503 discrete nodes and 579 edges, we .nd high diagnostic accuracy in scenarios where one to three faults, both in components and sensors, were inserted. The time taken to compute the most probable explanation using arithmetic circuits has a small mean of 0.2625 milliseconds and standard deviation of 0.2028 milliseconds. In experiments with data from ADAPT we also show that arithmetic circuit evaluation substantially outperforms joint tree propagation and variable elimination, two alternative algorithms for diagnosis using Bayesian network inference.

Mengshoel, Ole J.↗
DOE OSTI2019

Dynamic variable precision computation

A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

97 MATHEMATICS AND COMPUTING↗