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At least 91 records · Page 5

Phase-locked loop FM demodulator

A conventional phase-locked loop is improved by replacing its phase detector with one comprising a linear ramp generator and a sample-and-hold circuit, thus eliminating the need for a lowpass loop filter, although the output of the sample-and-hold circuit may be filtered in the case of a very low level modulating signal on the incoming FM signal, but then filtering is not a difficult problem as in a conventional phase-locked loop. The result is FM demodulation by zero-order estimation. For FM demodulation by first-order estimation, the arithmetic difference between adjacent samples is formed, and using a second sample-and-hold circuit an arithmetic difference signal is produced as an input to a second ramp generator that is reset after each sampling cycle to generate a ramp the slope of which is a function of the arithmetic difference signal stored in the second sample-and-hold circuit. The ramp thus generated by the second ramp generator is arithmetically summed with the zero-estimation signal from the first sample-and-hold circuit to form a first-order estimation signal. Filtering such a first-order estimation signal is less of a problem than filtering a zero-order estimation signal.

Kirkham, Harold↗

Fault tolerant computing: A preamble for assuring viability of large computer systems

The need for fault-tolerant computing is addressed from the viewpoints of (1) why it is needed, (2) how to apply it in the current state of technology, and (3) what it means in the context of the Phoenix computer system and other related systems. To this end, the value of concurrent error detection and correction is described. User protection, program retry, and repair are among the factors considered. The technology of algebraic codes to protect memory systems and arithmetic codes to protect memory systems and arithmetic codes to protect arithmetic operations is discussed.

Lim, R. S.↗

Research in the design of high-performance reconfigurable systems

An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.

Slotnick, D. L.↗

Research in the design of high-performance reconfigurable systems

The initial control and programming philosophies of the RELAPSE are discussed. A block diagram showing the relationship of the Arithmetic Units (composed of Stages and Bit Processors), to the Functional Units, and other components of the RELAPSE is used to guide this discussion. The latest version of the Bit Processor design is presented. Included is a detailed discussion of the Bit Processor's new scratch pad memory component. The section also clarifies the usage of the Bit Processor's processing registers, and Input/Output functions. The final design phase of the Arithmetic Unit is underway by a study of the Proposed IEEE Floating Point Standard. The decisions on conformation to this standard will be used as inputs into the finalization of the designs of the Bit Processor, Stage, and Arithmetic Units of the RELAPSE.

Slotnick, D. L.↗

Noiseless compression using non-Markov models

Adaptive data compression techniques can be viewed as consisting of a model specified by a database common to the encoder and decoder, an encoding rule and a rule for updating the model to ensure that the encoder and decoder always agree on the interpretation of the next transmission. The techniques which fit this framework range from run-length coding, to adaptive Huffman and arithmetic coding, to the string-matching techniques of Lempel and Ziv. The compression obtained by arithmetic coding is dependent on the generality of the source model. For many sources, an independent-letter model is clearly insufficient. Unfortunately, a straightforward implementation of a Markov model requires an amount of space exponential in the number of letters remembered. The Directed Acyclic Word Graph (DAWG) can be constructed in time and space proportional to the text encoded, and can be used to estimate the probabilities required for arithmetic coding based on an amount of memory which varies naturally depending on the encoded text. The tail of that portion of the text which was encoded is the longest suffix that has occurred previously. The frequencies of letters following these previous occurrences can be used to estimate the probability distribution of the next letter. Experimental results indicate that compression is often far better than that obtained using independent-letter models, and sometimes also significantly better than other non-independent techniques.

Blumer, Anselm↗

Basic mathematical function libraries for scientific computation

Ada packages implementing selected mathematical functions for the support of scientific and engineering applications were written. The packages provide the Ada programmer with the mathematical function support found in the languages Pascal and FORTRAN as well as an extended precision arithmetic and a complete complex arithmetic. The algorithms used are fully described and analyzed. Implementation assumes that the Ada type FLOAT objects fully conform to the IEEE 754-1985 standard for single binary floating-point arithmetic, and that INTEGER objects are 32-bit entities. Codes for the Ada packages are included as appendixes.

Galant, David C.↗

A 640-MHz 32-megachannel real-time polyphase-FFT spectrum analyzer

A polyphase fast Fourier transform (FFT) spectrum analyzer being designed for NASA's Search for Extraterrestrial Intelligence (SETI) Sky Survey at the Jet Propulsion Laboratory is described. By replacing the time domain multiplicative window preprocessing with polyphase filter processing, much of the processing loss of windowed FFTs can be eliminated. Polyphase coefficient memory costs are minimized by effective use of run length compression. Finite word length effects are analyzed, producing a balanced system with 8 bit inputs, 16 bit fixed point polyphase arithmetic, and 24 bit fixed point FFT arithmetic. Fixed point renormalization midway through the computation is seen to be naturally accommodated by the matrix FFT algorithm proposed. Simulation results validate the finite word length arithmetic analysis and the renormalization technique.

Zimmerman, G. A.↗

A seismic data compression system using subband coding

This article presents a study of seismic data compression techniques and a compression algorithm based on subband coding. The algorithm includes three stages: a decorrelation stage, a quantization stage that introduces a controlled amount of distortion to allow for high compression ratios, and a lossless entropy coding stage based on a simple but efficient arithmetic coding method. Subband coding methods are particularly suited to the decorrelation of nonstationary processes such as seismic events. Adaptivity to the nonstationary behavior of the waveform is achieved by dividing the data into separate blocks that are encoded separately with an adaptive arithmetic encoder. This is done with high efficiency due to the low overhead introduced by the arithmetic encoder in specifying its parameters. The technique could be used as a progressive transmission system, where successive refinements of the data can be requested by the user. This allows seismologists to first examine a coarse version of waveforms with minimal usage of the channel and then decide where refinements are required. Rate-distortion performance results are presented and comparisons are made with two block transform methods.

Kiely, A. B.↗

Using EEG To Detect and Monitor Mental Fatigue

This project aims to develop EEG-based methods for detecting and monitoring mental fatigue. Mental fatigue poses a serious risk, even when performance is not apparently degraded. When such fatigue is associated with sustained performance of a single type of cognitive task it may be related to the metabolic energy required for sustained activation of cortical areas specialized for that task. The objective of this study was to adapt EEG to monitor cortical energy over a long period of performance of a cognitive task. Multielectrode event related potentials (ERPs) were collected every 15 minutes in nine subjects who performed a mental arithmetic task (algebraic sum of four randomly generated negative or positive digits). A new problem was presented on a computer screen 0.5 seconds after each response; some subjects endured for as long as three hours. ERPs were transformed to a quantitative measure of scalp electrical field energy. The average energy level at electrode P3 (near the left angular gyrus), 100-300 msec latency, was compared over the series of ERPs. For most subjects, scalp energy density at P3 gradually fell over the period of task performance and dramatically increased just before the subject was unable to continue the task. This neural response can be simulated for individual subjects using, a differential equation model in which it is assumed that the mental arithmetic task requires a commitment of metabolic energy that would otherwise be used for brain activities that are temporarily neglected. Their cumulative neglect eventually requires a reallocation of energy away from the mental arithmetic task.

Montgomery, Leslie↗

Model-Checking with Edge-Valued Decision Diagrams

We describe an algebra of Edge-Valued Decision Diagrams (EVMDDs) to encode arithmetic functions and its implementation in a model checking library along with state-of-the-art algorithms for building the transition relation and the state space of discrete state systems. We provide efficient algorithms for manipulating EVMDDs and give upper bounds of the theoretical time complexity of these algorithms for all basic arithmetic and relational operators. We also demonstrate that the time complexity of the generic recursive algorithm for applying a binary operator on EVMDDs is no worse than that of Multi-Terminal Decision Diagrams. We have implemented a new symbolic model checker with the intention to represent in one formalism the best techniques available at the moment across a spectrum of existing tools: EVMDDs for encoding arithmetic expressions, identity-reduced MDDs for representing the transition relation, and the saturation algorithm for reachability analysis. We compare our new symbolic model checking EVMDD library with the widely used CUDD package and show that, in many cases, our tool is several orders of magnitude faster than CUDD.

Roux, Pierre↗

A Comparative Study of Randomized Constraint Solvers for Random-Symbolic Testing

The complexity of constraints is a major obstacle for constraint-based software verification. Automatic constraint solvers are fundamentally incomplete: input constraints often build on some undecidable theory or some theory the solver does not support. This paper proposes and evaluates several randomized solvers to address this issue. We compare the effectiveness of a symbolic solver (CVC3), a random solver, three hybrid solvers (i.e., mix of random and symbolic), and two heuristic search solvers. We evaluate the solvers on two benchmarks: one consisting of manually generated constraints and another generated with a concolic execution of 8 subjects. In addition to fully decidable constraints, the benchmarks include constraints with non-linear integer arithmetic, integer modulo and division, bitwise arithmetic, and floating-point arithmetic. As expected symbolic solving (in particular, CVC3) subsumes the other solvers for the concolic execution of subjects that only generate decidable constraints. For the remaining subjects the solvers are complementary.

Takaki, Mitsuo↗

Automatic Generation of Guard-Stable Floating-Point Code

In floating-point programs, test instability occurs when the control flow of a conditional statement diverges from its ideal execution under real arithmetic. This phenomenon is caused by the presence of round-off errors in floating-point computations. Writing programs that correctly handle test instability often require expertise on finite precision computations and rounding errors. This paper presents a fully automatic tool chain that generates and formally verifies a test-stable floating-point C program from its functional specification in real arithmetic. The generated program is instrumented to soundly detect when unstable tests may occur and, in these cases, to issue a warning. The proposed approach combines the PRECiSA floating-point static analyzer, the Frama-C software verification suite, and the PVS theorem prover.

Floating-Point Arithmetic↗

Extended precision software packages

A description of three extended precision packages is presented along with three small conversion subroutines which can be used in conjunction with the extended precision packages. These extended packages represent software packages written in FORTRAN 4. They contain normalized or unnormalized floating point arithmetic with symmetric rounding and arbitrary mantissa lengths, and normalized floating point interval arithmetic with appropriate rounding. The purpose of an extended precision package is to enable the user to use and manipulate numbers with large decimal places as well as those with small decimal places where precision beyond double precision is required.

Phillips, E. J.↗

Low-cost coding techniques for digital fault diagnosis

Published report discusses fault location properties of arithmetic codes. Criterion for effectiveness of given code is detection probability of local fault by application of checking algorithm to results of entire set of algorithms of processor. Report also presents analysis of arithmetic codes with low-cost check algorithm which possesses partial fault-location properties.

Avizienis, A. A.↗

Some observed seasonal changes in extratropical general circulation: A study in terms of vorticity

Extratropical eddy distributions in four months typical of the four seasons are treated in terms of temporal mean and temporal r.m.s. values of the geostrophic relative vorticity. The geographical distributions of these parameters at the 300 mb level show that the arithmetic mean fields are highly biased representatives of the extratropical eddy distributions. The zonal arithmetic means of these parameters are also presented. These show that the zonal-and-time mean relative vorticity is but a small fraction of the zonal mean of the temporal r.m.s. relative vorticity, K. The reasons for considering the r.m.s. values as the temporal normal values of vorticity in the extratropics are given in considerable detail. The parameter K is shown to be of considerable importance in locating the extratropical frontal jet streams (EFJ) in time-and-zonal average distributions. The study leads to an understanding of the seasonal migrations of the EFJ which have not been explored until now.

Srivatsangam, S.↗

Architecture and data processing alternatives for the TSE computer. Volume 2: Extraction of topological information from an image by the Tse computer

A simple programmable Tse processor organization and arithmetic operations necessary for extraction of the desired topological information are described. Hardware additions to this organization are discussed along with trade-offs peculiar to the tse computing concept. An improved organization is presented along with the complementary software for the various arithmetic operations. The performance of the two organizations is compared in terms of speed, power, and cost. Software routines developed to extract the desired information from an image are included.

Jones, J. R.↗

Applications of satellite technology for regional organizations (Project ASTRO)

The direct arithmetic processing of adaptive delta modulation (ADM) encoded signals, conversion from ADM encoded signals to pulse code modulation (PCM) encoded signals, and conversion from PCM to ADM encoded signals are discussed. It is shown that signals which are ADM encoded can be arithmetically processed directly, without first decoding. Operating on the DM bit stream, and employing only standard digital hardware, the sum, difference and product can be obtained in PCM and ADM format.

Schilling, D. L.↗

Suggested architecture for a specialized fluid dynamics computer

Future flow simulations in 3-D will require computers with extremely large main memories and an advantageous ratio between computer cost and arithmetic speed. Since random access memories are very expensive, a pipeline design is proposed which allows the use of much cheaper sequential devices without any sacrifice in speed for vector references (even with arbitrary spacing between successive elements). Also scalar arithmetic can be performed efficiently. The comparatively low speed of the proposed machine (about 10 to the 7th power operations per second) would be offset by a very low price per unit, making mass production possible.

Fornberg, B.↗