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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Toward ultrafast, ultra-stable imaging arrays: Superlattice doping to enhance the performance of backside-illuminated 3D-hybridized silicon photodetectors

In this paper, the authors report the latest results on their development of superlattice-doped, thinned, backside-illuminated (BSI), 3D-integrated photodiode detectors—a step toward their ultimate goal of demonstrating ultrafast, ultrastable CMOS imaging arrays. As with most silicon-based photodetectors, backside-illumination and backside surface passivation are keys to achieve the highest performance capability. The two-dimensional (2D) doping technique developed at the Jet Propulsion Laboratory (JPL) has proved to result in a highly efficient, highly stable detector response when combined with a variety of detectors. Here, JPL's 2D-doping has been combined with Sandia's BSI photodetectors hybridized with custom fanout wafer via copper Direct Bond Interconnect (DBI®), a technology that is rapidly becoming industry standard for BSI CMOS imaging arrays. The prototype detectors were packaged and evaluated with respect to their response to low energy electrons. The authors find that the responsivity of 2D-doped BSI detectors is higher than devices prepared using other surface passivation techniques (i.e., ion implantation). The success of the work described herein verifies that the 2D-doping processes previously developed for Sandia's frontside-illuminated photodetectors are generally applicable to BSI detectors and demonstrates for the first time that JPL's 2D-doping process is compatible with the Cu-DBI® technology.

Jewell, April D.↗
DOE OSTI2020

Study of CMOS strip sensor for future silicon tracker

Monolithic silicon sensors developed with High-Voltage CMOS (HV-CMOS) processes have become highly attractive for charged particle tracking. Compared with the standard CMOS sensors, HV-CMOS sensors can provide larger and deeper depletion regions that lead to larger signals and faster charge collection. They can provide high position resolution, low material budget, high radiation hardness and low cost that are desirable for high performance tracking in harsh collision environment. Various studies have been conducted to explore the technology feasibility for the large-area tracking systems at future collider experiments. CHESS (CMOS HV/HR Evaluation for Strip Sensor) sensor series have been developed as an alternative solution to the conventional silicon micro-strip detectors for the ATLAS inner tracker upgrade. The first prototype (named CHESS1) was to evaluate the diode geometry and the in-pixel analog electronics. Obtained test results were used to optimize the second prototype (named CHESS2). CHESS2 was implemented with a full digital readout architecture and realized as a full reticle sized monolithic sensor. Here, the basic characteristics of the CHESS2 prototype sensors and their performance in response to different input signals are presented.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Development of CMOS Sensors for HEP with a US-based foundry

We will present a program to establish the first development and manufacturing of HEP-specific sensors monolithically integrated into a standard CMOS process using a US-based foundry. In collaboration with several US universities the project aims to develop Monolithic Active Pixel Sensors (MAPS) designs implemented in the 90 nm technology node, including simple test structures and multi-pixel arrays, and monolithic CMOS sensors with readout integrated circuits, perform detailed characterization of the detector prototypes and quantify their performance for HEP applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Gate-Tunable Short-Wave Infrared Polycrystalline GeSn Phototransistors on Noncrystalline Substrates

GeSn is a group-IV alloy with immense potential to advance microelectronics technology due to its intrinsic compatibility with existing Si CMOS processes. With a sufficiently high Sn composition, GeSn is classified as a direct bandgap semiconductor. Polycrystalline GeSn holds several additional advantages, including its significantly lower synthesis cost compared to its epitaxial counterpart, as well as the versatility to grow these films on a variety of substrates. Here, in this work, we present a polycrystalline thin-film GeSn phototransistor on a fused silica substrate with a Sn composition of ~10%, showing a photoresponse in the short-wave infrared wavelength range, critical for emerging sensing applications. This device shows a gate-tunable response, with responsivities approaching up to 1.7 mA/W with only a 30 nm-thick GeSn layer. Furthermore, phototransistors offer additional adaptability through gating, which allows for the reduction of dark current. This not only enhances the signal-to-noise ratio but also offers more flexible integration with various image sensor readout implementations using different substrates. The specific detectivity of this phototransistor is within an order of magnitude of those of previously reported GeSn photodetectors grown by molecular beam epitaxy and chemical vapor deposition, even though the absorber is 3 to 20× thinner while the electrode spacing for photocarrier transport is approximately 15× longer than the carrier diffusion length in this work, showing great potential benefits of extending similar device structures to epitaxial GeSn layers. As these GeSn phototransistors utilize a noncrystalline substrate, our work establishes a fundamentally more versatile path toward monolithically integrated GeSn-based photodetectors for next-generation multimodal sensors.

36 MATERIALS SCIENCE↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2025

Gigahertz-frequency acousto-optic phase modulation of visible light in a CMOS-fabricated photonic circuit

Optical phase modulators operating at visible wavelengths are essential components for photonic technologies such as those for quantum control, communications, and laser ranging. However, they remain challenging to implement in scalable, integrated platforms capable of handling high optical powers. Here we present a visible-light, gigahertz-frequency acousto-optic phase modulator, fabricated on a 200-mm wafer in a volume CMOS foundry, that supports greater than 500 mW of optical power at 730 nm. The device combines a piezoelectric transducer and a photonic waveguide within a single, wavelength-scale structure that confines both a propagating optical mode and an electrically excitable breathing-mode mechanical resonance. By tuning the device’s geometry to optimize the optomechanical interaction, we achieve modulation depths up to 4.85 rad with 80 mW of applied microwave power at 2.31 GHz in a 2-mm-long device. This corresponds to resonant modulation figures of merit of V π = 1.32V and V π ⋅ L = 0.26V cm. To our knowledge, this is the lowest V π ever demonstrated in any acousto-optic phase modulator and represents a 15-fold reduction in V π and a 100-fold reduction in required microwave power relative to state-of-the-art modulators with high visible-wavelength power handling commonly employed in quantum control systems.

Freedman, Jacob M. [Univ. of Arizona, Tucson, AZ (↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2021

Hybrid MEMS-CMOS ion traps for NISQ computing

Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. Finally, we also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Field‐Induced Ferroelectric Phase Evolution During Polarization “Wake‐Up” in Hf 0.5 Zr 0.5 O 2 Thin Film Capacitors

Abstract As an emerging nonvolatile memory technology, HfO 2 ‐based ferroelectrics exhibit excellent compatibility with silicon CMOS process flows; however, the reliability of polarization switching in these materials remains a major challenge. During repeated field programming and erase of the polarization state of initially pristine HfO 2 ‐based ferroelectric capacitors, the magnitude of the measured polarization increases, a phenomenon known as “wake‐up”. In this study, the authors attempt to understand what causes the wake‐up effect in Hf 0.5 Zr 0.5 O 2 (HZO) capacitors using nondestructive methods that probe statistically significant sample volumes. Synchrotron X‐ray diffraction reveals a concerted shift in HZO Bragg peak position as a function of polarization switching cycle number in films prepared under conditions such that they exhibit extremely large (≈3000%) wake‐up. In contrast, a control sample with insignificant wake‐up shows no such peak shift. Capacitance – voltage measurements show evolution in the capacitance loop with switching cycle number for the wake‐up sample and no change for the control sample. Piezoresponse force microscopy measurements are utilized to visualize the domain switching with wake‐up. The combination of these observations clearly demonstrates that wake‐up is caused by a field‐driven phase transformation of the tetragonal phase to the metastable ferroelectric orthorhombic phase during polarization switching of HZO capacitors.

36 MATERIALS SCIENCE↗
DOE OSTI2026

ALD-Derived WO 3– x Leads to Nearly Wake-Up-Free Ferroelectric Hf 0.5 Zr 0.5 O 2 at Elevated Temperatures

Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics─either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures, such as 125°C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO 2 -based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO 3–x ) layer─known as an oxygen reservoir─and carefully tuning its oxygen content, ultrathin Hf 0.5 Zr 0.5 O 2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 10 5 to only 10 at 125°C, a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory (DFT) calculations reveal that WO 3 enhances the stability of the ferroelectric orthorhombic phase (o-phase) at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.

36 MATERIALS SCIENCE↗
DOE OSTI2020

PbE (E = S, Se) Colloidal Quantum Dot-Layered 2D Material Hybrid Photodetectors

Hybrid lead chalcogenide (PbE) (E = S, Se) quantum dot (QD)-layered 2D systems are an emerging class of photodetectors with unique potential to expand the range of current technologies and easily integrate into current complementary metal-oxide-semiconductor (CMOS)-compatible architectures. Herein, we review recent advancements in hybrid PbE QD-layered 2D photodetectors and place them in the context of key findings from studies of charge transport in layered 2D materials and QD films that provide lessons to be applied to the hybrid system. Photodetectors utilizing a range of layered 2D materials including graphene and transition metal dichalcogenides sensitized with PbE QDs in various device architectures are presented. Figures of merit such as responsivity (R) and detectivity (D*) are reviewed for a multitude of devices in order to compare detector performance. Finally, a look to the future considers possible avenues for future device development, including potential new materials and device treatment/fabrication options.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Thermally generated magnonic spin currents in a polycrystalline gadolinium iron garnet thin film with perpendicular magnetic anisotropy

Rare-earth iron garnets (REIGs) are the benchmark systems for magnonics, including the longitudinal spin Seebeck effect (LSSE). While most research has focused on single-crystalline REIGs on complimentary garnet substrates, moving to more, cost-effective complementary metal-oxide semiconductor (CMOS)-compatible substrates is important to integrate REIG thin films with existing technology. In this regard, we grow a 130 nm-thick polycrystalline gadolinium iron garnet (GdIG) film on the Si/SiO2 substrate and investigate the temperature-dependent LSSE. Interestingly, the polycrystalline GdIG film exhibits perpendicular magnetic anisotropy (PMA) at room temperature which is induced by tensile in-plane (IP)-strain originating from the thermal-expansion mismatch between the GdIG film and the substrate during rapid thermal annealing. Further, a spin-reorientation transition from the out-of-plane IP direction below TS = 180 K is observed. Additionally, the film reveals a magnetic compensation temperature, TComp, of ≈240 K. The LSSE voltage not only demonstrates a sign-inversion around TComp, but also shows noticeable changes around TS. As compared to a single-crystalline GdIG film, the lower LSSE voltage for the polycrystalline GdIG is attributed to the higher effective magnetic anisotropy and enhanced magnon scattering at the grain boundaries. Our study not only paves the way for the cost-effective growth of CMOS-compatible REIG-based systems with PMA for magnonic memory and information processing applications, but also highlights the fact that the spincaloritronic and spin-insulatronic properties of the polycrystalline REIGs follow those of their single-crystalline counterparts with reduced spin-to-charge conversion efficiency through LSSE which can be tuned further by controlling the average gran size and interface engineering.

Physics↗
DOE OSTI2026

Phase Synergy Enables Low‐Power Ferroelectric Switching in HfO 2 Epitaxial Films

HfO 2 -based ferroelectric materials have emerged as leading candidates for next-generation non-volatile memory technologies, owing to their nanoscale robust ferroelectricity and complementary metal–oxide–semiconductor (CMOS) compatibility. However, challenges and debates persist in advancing and comprehensively understanding their ferroelectric behavior. In particular, conventional approaches typically regard non-ferroelectric phases as detrimental and primarily focus on suppressing their formation, yet overlooking their potentially synergistic contributions—particularly those of the tetragonal (T) phase. Here, we unambiguously clarify the beneficial role of the T-phase and introduce a phase-boundary engineering strategy that deliberately harnesses it to enhance ferroelectricity in HfO 2 films. By stabilizing optimal coherent boundaries between ferroelectric orthorhombic (O) and T phases in epitaxial La-doped HfO 2 films, we achieve significant improvements in ferroelectric properties—doubling the remanent polarization (P r ∼ 30 µC/cm 2 ) and substantially reducing the coercive field (E c ∼ 3 MV/cm) by 30% compared to low-La doped samples without such boundaries. Atomic-scale electron microscopy reveals the structural nature of the atomically sharp, coherent O–T boundaries. Combined with deep-learning enhanced molecular dynamics simulations, our results unravel that these boundaries facilitate intermediate polarization states that lower the switching energy barrier. Consequently, phase coexistence shifts from an inherent drawback to a tunable design element, offering a broadly applicable route to ultra-low-power HfO 2 -based nanoelectronics.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

CMOS-Based Single-Cycle in-Memory XOR/XNOR

Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2× improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2024

STOPGAP—A time-of-flight extension for the Belle II TOP barrel PID system

The Belle II barrel region is instrumented with the Time of Propagation (TOP) particle identification system. Due to its mechanical design, the individual TOP modules do not overlap, leaving a gap of around 2 cm between them in the azimuthal direction. This leads to a 6%–9% drop in acceptance, depending on the track’s momentum. We propose a solution to remedy these gaps by instrumenting them with fast silicon detectors to directly measure the time-of-flight of traversing particles. We present here a simulation study discussing the performance requirements and the possible sensor technologies, and we demonstrate that such a project could be realized with novel, fast monolithic CMOS sensors, or alternatively AC-LGAD sensors, both of which are expected to reach MIP timing resolutions of down to 50 ps or better.

Hartbrich, Oskar↗
DOE OSTI2023

Milestone report for MRT 8479: High Yield Xray Imager Preliminary Design Review

The High Yield Xray Imager (HYXI) is a new NIF target diagnostic system currently under development. The goal of HYXI is to provide high-fidelity, high temporal resolution x-ray imaging capability on high yield NIF implosions at 10MJ and above. The HYXI instrument design concept is based on the combination of two technologies that have been successfully utilized at the NIF on previous instruments, electron pulse-dilation and hybrid-CMOS sensor imaging. The combination of these two techniques will give HYXI sufficient data quality to ascertain differences in hot spot formation dynamics between high and low yield implosions. This information will highlight the critical hot spot conditions needed for ignition and burn. The HYXI design leverages the successful operation of the PDIXI x-ray imager at the NIF on multi-MJ yield shots. Also, a new radiation tolerance CMOS imaging array is being developed to eliminate the significant background noise which limits the data quality of PDIXI. The HYXI Preliminary Design Review was completed at the end of Q4 FY23. The HYXI project is a multi-year effort with a phased approach to be bring up system functionality over time in parallel with the development and fabrication effort of the new CMOS imaging array. Initial time integrated NIF data will be collected in Q2 FY25, first time resolved imaging with Daedalus starting in Q2 FY26 and the final performance qualification of the complete HYXI system is scheduled for Q2 FY27.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Piezoelectrically actuated silicon-nitride-based high-speed spatial light modulator

Advancements in light modulator technology have been driving discoveries and progress across various fields. The problem of large-scale coherent optical control of atomic quantum systems—including cold atoms, ions, and solid-state color centers—presents among the most stringent requirements. This motivates a new generation of high-speed large-scale modulator technology operating in the visible to near-infrared wavelength range. We introduce a scalable modulator technology based on piezoelectrically actuated silicon nitride resonant waveguide gratings fabricated on 200 mm diameter silicon wafers with CMOS-compatible processes. We present a proof-of-concept device with 4 × 4 individually addressable 50 μ m × 50 μ m pixels or channels, each containing a resonant waveguide grating with a ~ 780 nm design wavelength, supporting > 100 MHz modulation speeds, and a spectral response with > 20 dB extinction.

integrated optics↗