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At least 91 records · Page 5

A measurement-based study of concurrency in a multiprocessor

A systematic measurement-based methodology for characterizing the amount of concurrency present in a workload, and the effect of concurrency on system performance indices such as cache miss rate and bus activity are developed. Hardware and software instrumentation of an Alliant FX/8 was used to obtain data from a real workload environment. Results show that 35% of the workload is concurrent, with the concurrent periods typically using all available processors. Measurements of periods of change in concurrency show uneven usage of processors during these times. Other system measures, including cache miss rate and processor bus activity, are analyzed with respect to the concurrency measures. Probability of a cache miss is seen to increase with concurrency. The change in cache miss rate is much more sensitive to the fraction of concurrent code in the worklaod than the number of processors active during concurrency. Regression models are developed to quantify the relationships between cache miss rate, bus activity, and the concurrency measures. The model for cache miss rate predicts an increase in the median miss rate value as much as 300% for a 100% increase in concurrency in the workload.

Mcguire, Patrick John↗

Using Minimum-Surface Bodies for Iteration Space Partitioning

A number of known techniques for improving cache performance in scientific computations involve the reordering of the iteration space. Some of these reorderings can be considered as coverings of the iteration space with the sets having good surface-to-volume ratio. Use of such sets reduces the number of cache misses in computations of local operators having the iteration space as a domain. We study coverings of iteration spaces represented by structured and unstructured grids. For structured grids we introduce a covering based on successive minima tiles of the interference lattice of the grid. We show that the covering has good surface-to-volume ratio and present a computer experiment showing actual reduction of the cache misses achieved by using these tiles. For unstructured grids no cache efficient covering can be guaranteed. We present a triangulation of a 3-dimensional cube such that any local operator on the corresponding grid has significantly larger number of cache misses than a similar operator on a structured grid.

Frumlin, Michael↗

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

Liu, Yuan-Kwei↗

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial change to the current DMS design at this time.

Liu, Yuan-Kwei↗

An effective write policy for software coherence schemes

The authors study the write behavior and evaluate the performance of various write strategies and buffering techniques for a MIN-based multiprocessor system using the simple software coherence scheme. Hit ratios, memory latencies, total execution time, and total write traffic are used as the performance indices. The write-through write-allocate no-fetch cache using a write-back write buffer is shown to have a better performance than both write-through and write-back caches. This type of write buffer is effective in reducing the volume as well as bursts of write traffic. On average, the use of a write-back cache reduces by 60 percent the total write traffic generated by a write-through cache.

Chen, Yung-Chin↗

Initial Performance Results on IBM POWER6

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Saini, Subbash↗

Mobile Thread Task Manager

The Mobile Thread Task Manager (MTTM) is being applied to parallelizing existing flight software to understand the benefits and to develop new techniques and architectural concepts for adapting software to multicore architectures. It allocates and load-balances tasks for a group of threads that migrate across processors to improve cache performance. In order to balance-load across threads, the MTTM augments a basic map-reduce strategy to draw jobs from a global queue. In a multicore processor, memory may be "homed" to the cache of a specific processor and must be accessed from that processor. The MTTB architecture wraps access to data with thread management to move threads to the home processor for that data so that the computation follows the data in an attempt to avoid L2 cache misses. Cache homing is also handled by a memory manager that translates identifiers to processor IDs where the data will be homed (according to rules defined by the user). The user can also specify the number of threads and processors separately, which is important for tuning performance for different patterns of computation and memory access. MTTM efficiently processes tasks in parallel on a multiprocessor computer. It also provides an interface to make it easier to adapt existing software to a multiprocessor environment.

Clement, Bradley J.↗

Advanced Curation: Solving Current and Future Sample Return Problems

Advanced Curation is a wide-ranging and comprehensive research and development effort at NASA Johnson Space Center that identifies and remediates sample related issues. For current collections, Advanced Curation investigates new cleaning, verification, and analytical techniques to assess their suitability for improving curation processes. Specific needs are also assessed for future sample return missions. For each need, a written plan is drawn up to achieve the requirement. The plan draws while upon current Curation practices, input from Curators, the analytical expertise of the Astromaterials Research and Exploration Science (ARES) team, and suitable standards maintained by ISO, IEST, NIST and other institutions. Additionally, new technologies are adopted on the bases of need and availability. Implementation plans are tested using customized trial programs with statistically robust courses of measurement, and are iterated if necessary until an implementable protocol is established. Upcoming and potential NASA missions such as OSIRIS-REx, the Asteroid Retrieval Mission (ARM), sample return missions in the New Frontiers program, and Mars sample return (MSR) all feature new difficulties and specialized sample handling requirements. The Mars 2020 mission in particular poses a suite of challenges since the mission will cache martian samples for possible return to Earth. In anticipation of future MSR, the following problems are among those under investigation: What is the most efficient means to achieve the less than 1.0 ng/sq cm total organic carbon (TOC) cleanliness required for all sample handling hardware? How do we maintain and verify cleanliness at this level? The Mars 2020 Organic Contamination Panel (OCP) predicts that organic carbon, if present, will be present at the "one to tens" of ppb level in martian near-surface samples. The same samples will likely contain wt% perchlorate salts, or approximately 1,000,000x as much perchlorate oxidizer as organic carbon. The chemical kinetics of this reaction are poorly understood at present under the conditions of cached or curated martian samples. Among other parameters, what is the maximum temperature allowed during storage in order to preserve native martian organic compounds for analysis? What is the best means to collect headspace gases from cached martian (and other) samples? This gas will contain not only martian atmosphere but also off-gassed volatiles from the cached solids.

Fries, M.↗

Is random access memory random?

Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

Denning, P. J.↗

Prefetching in file systems for MIMD multiprocessors

The question of whether prefetching blocks on the file into the block cache can effectively reduce overall execution time of a parallel computation, even under favorable assumptions, is considered. Experiments have been conducted with an interleaved file system testbed on the Butterfly Plus multiprocessor. Results of these experiments suggest that (1) the hit ratio, the accepted measure in traditional caching studies, may not be an adequate measure of performance when the workload consists of parallel computations and parallel file access patterns, (2) caching with prefetching can significantly improve the hit ratio and the average time to perform an I/O (input/output) operation, and (3) an improvement in overall execution time has been observed in most cases. In spite of these gains, prefetching sometimes results in increased execution times (a negative result, given the optimistic nature of the study). The authors explore why it is not trivial to translate savings on individual I/O requests into consistently better overall performance and identify the key problems that need to be addressed in order to improve the potential of prefetching techniques in the environment.

Kotz, David F.↗

Empirical study of parallel LRU simulation algorithms

This paper reports on the performance of five parallel algorithms for simulating a fully associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are SIMD, and are implemented on the MasPar MP-2 architecture. Two other algorithms are parallelizations of an efficient serial algorithm on the Intel Paragon. One SIMD algorithm is quite simple, but its cost is linear in the cache size. The two other SIMD algorithm are more complex, but have costs that are independent on the cache size. Both the second and third SIMD algorithms compute all stack distances; the second SIMD algorithm is completely general, whereas the third SIMD algorithm presumes and takes advantage of bounds on the range of reference tags. Both MIMD algorithm implemented on the Paragon are general and compute all stack distances; they differ in one step that may affect their respective scalability. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC benchmark programs.

Carr, Eric↗

Becoming Reactive by Concretization

One way to build a reactive system is to construct an action table indexed by the current situation or stimulus. The action table describes what course of action to pursue for each situation or stimulus. This paper describes an incremental approach to constructing the action table through achieving goals with a hierarchical search system. These hierarchies are generated with transformations called concretizations, which add constraints to a problem and which can reduce the search space. The basic idea is that an action for a state is looked up in the action table and executed whenever the action table has an entry for that state; otherwise, a path is found to the nearest (cost-wise in a graph with costweighted arcs) state that has a mappring from a state in the next highest hierarchy. For each state along the solution path, the successor state in the path is cached in the action table entry for that state. Without caching, the hierarchical search system can logarithmically reduce search. When the table is complete the system no longer searches: it simply reacts by proceeding to the state listed in the table for each state. Since the cached information is specific only to the nearest state in the next highest hierarchy and not the goal, inter-goal transfer of reactivity is possible. To illustrate our approach, we show how an implemented hierarchical search system can completely reactive.

Prieditis, Armand↗

The Science of Computing: Virtual Memory

In the March-April issue, I described how a computer's storage system is organized as a hierarchy consisting of cache, main memory, and secondary memory (e.g., disk). The cache and main memory form a subsystem that functions like main memory but attains speeds approaching cache. What happens if a program and its data are too large for the main memory? This is not a frivolous question. Every generation of computer users has been frustrated by insufficient memory. A new line of computers may have sufficient storage for the computations of its predecessor, but new programs will soon exhaust its capacity. In 1960, a longrange planning committee at MIT dared to dream of a computer with 1 million words of main memory. In 1985, the Cray-2 was delivered with 256 million words. Computational physicists dream of computers with 1 billion words. Computer architects have done an outstanding job of enlarging main memories yet they have never kept up with demand. Only the shortsighted believe they can.

Denning, Peter J.↗

ROPEC - ROtary PErcussive Coring Drill for Mars Sample Return

The ROtary Percussive Coring Drill is a light weight, flight-like, five-actuator drilling system prototype designed to acquire core material from rock targets for the purposes of Mars Sample Return. In addition to producing rock cores for sample caching, the ROPEC drill can be integrated with a number of end effectors to perform functions such as rock surface abrasion, dust and debris removal, powder and regolith acquisition, and viewing of potential cores prior to caching. The ROPEC drill and its suite of end effectors have been demonstrated with a five degree of freedom Robotic Arm mounted to a mobility system with a prototype sample cache and bit storage station.

Chu, Philip↗

X-Ray Computed Tomography: The First Step in Mars Sample Return Processing

The Mars 2020 rover mission will collect and cache samples from the martian surface for possible retrieval and subsequent return to Earth. If the samples are returned, that mission would likely present an opportunity to analyze returned Mars samples within a geologic context on Mars. In addition, it may provide definitive information about the existence of past or present life on Mars. Mars sample return presents unique challenges for the collection, containment, transport, curation and processing of samples [1] Foremost in the processing of returned samples are the closely paired considerations of life detection and Planetary Protection. In order to achieve Mars Sample Return (MSR) science goals, reliable analyses will depend on overcoming some challenging signal/noise-related issues where sparse martian organic compounds must be reliably analyzed against the contamination background. While reliable analyses will depend on initial clean acquisition and robust documentation of all aspects of developing and managing the cache [2], there needs to be a reliable sample handling and analysis procedure that accounts for a variety of materials which may or may not contain evidence of past or present martian life. A recent report [3] suggests that a defined set of measurements should be made to effectively inform both science and Planetary Protection, when applied in the context of the two competing null hypotheses: 1) that there is no detectable life in the samples; or 2) that there is martian life in the samples. The defined measurements would include a phased approach that would be accepted by the community to preserve the bulk of the material, but provide unambiguous science data that can be used and interpreted by various disciplines. Fore-most is the concern that the initial steps would ensure the pristine nature of the samples. Preliminary, non-invasive techniques such as computed X-ray tomography (XCT) have been suggested as the first method to interrogate and characterize the cached samples without altering the materials [1,2]. A recent report [4] indicates that XCT may minimally alter samples for some techniques, and work is needed to quantify these effects, maximizing science return from XCT initial analysis while minimizing effects.

Welzenbach, L. C.↗

Organic and inorganic contamination control approaches for return sample investigation on Mars 2020

The Mars 2020 Rover mission will have the capability to collect and cache samples for potential Mars sample return. Specifically, the sample caching system (SCS) is designed for coring Mars samples and acquiring regolith samples as well as handling, sealing and caching on Mars. As the potential first Martian samples that could be returned to Earth, assuring low levels of terrestrial contamination is of the utmost concern. In developing the SCS, the project prioritizes limiting sample contamination in organic, inorganic and biological areas. The focus of this paper is on the strategies being implemented to limit terrestrial organic and inorganic contamination in the samples.

Steltzner, Adam↗

Identifying Shocked Feldspar on Mars Using Perseverance Spectroscopic Instruments: Implications for Geochronology Studies on Returned Samples

The Perseverance rover (Mars 2020) mission, the first step in NASA’s Mars Sample Return (MSR) program, will select samples for caching based on their potential to improve understanding Mars’ astrobiological, geological, geochemical, and climatic evolution. Geochronologic analyses will be among the key measurements planned for returned samples. Assessing a sample’s shock history will be critical because shock metamorphism could influence apparent sample age. Shock effects in one Mars-relevant mineral class, plagioclase feldspar, have been well- documented using various spectroscopy techniques (thermal infrared reflectance, emission, and transmission spectroscopy, Raman, and luminescence). A subset of these data will be obtained with the SuperCam and SHERLOC (Scanning Habitable Environments with Raman & Luminescence for Organics & Chemicals) instruments onboard Perseverance to inform caching decisions for MSR. Here, we review shock indicators in plagioclase feldspar as revealed in Raman, luminescence, and IR spectroscopy lab data, with an emphasis on Raman spectroscopy. We consider how this information may inform caching decisions for selecting optimal samples for geochronology measurements. We then identify challenges and make recommendations for both in situ measurements performed with SuperCam and SHERLOC and for supporting lab studies to enhance the success of geochronologic analyses after return to Earth.

mars↗

A Minority Report Submitted as an Addendum to the Report of the Mars 2020 Organic Contamination Panel

This Minority Report (MR) presents seven findings in addition to or contrary to the main OCP report: 1. Contamination control for the Mars 2020 cache must be strict. Mars’ surface is known to be organics-poor from laboratory studies, Mars meteorite analyses, and from four previous NASA missions. It is imperative that contamination control measures are enacted that enable reliable and robust detection of potential biomarker compounds at the ppb level. 2. Since Mars 2020 is a sample return mission and analyses of samples in the returnable cache are expected to occur after return to Earth, positive controls are not recommended for flight on Mars 2020 unless a compelling case can be made for their use. 3. The findings of previous panels dedicated to organic compound analysis in Martian samples (OCSSG, ND-SAG, SDT) recommend TOC limits between 10-40 ppb. The MR finds that the lower limit of 10 ppb is recommended and that insufficient justification is given by the OCP Panel Report (PR) to raise the TOC limit to 40 ppb. 4. Analytical capability is sufficiently advanced that analytical capability is an irrelevant consideration with respect to differentiating between 10 and 40 ppb TOC. 5. Perceived contamination control challenges are an irrelevant consideration for raising the TOC contamination limit from 10 to 40 ppb since those challenges, and the procedures to ameliorate them, will exist regardless of whether the limit is 10 or 40 ppb. 6. The “dilution cleaning” method has not been adequately proven for utilization on the Mars 2020 mission. Shortcomings have been identified in terms of peer review, method verification, analytical and testing approach, application to space flight hardware, and performance under Martian conditions. The method should be revisited and independently tested using statistically and analytically robust methods, and scrutinized in a rigorous peer review process. 7. The Mars 2020 mission claims considerable heritage from the Mars Science Laboratory (MSL) mission, but MSL contamination control efforts contain significant errors and implementation discrepancies that would imperil the Mars 2020 caching mission were they repeated. A standing contamination control panel should be formed to provide independent oversight for the Mars 2020 mission.

Mars Sample Return↗