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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

On-Chip Power-Combining for High-Power Schottky Diode Based Frequency Multipliers

A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

Siles Perez, Jose Vicente↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRS2020

Organic flip chip reliability study for space applications

The current state-of-the-art flip chip packages for space applications are the class-Y non-hermetic ceramic packages, whereas for commercial applications, organic packages have been the mainstream technology for about two decades. The high reliability of the class-Y parts suggests that the hermeticity is not critical for the reliability of flip chip devices and that organic flip chip packages could be reliable enough for space applications. The current report summarizes the result of collaboration between JPL and Cobham semiconductor space solutions to study the reliability of the organic flip chip packages.

Measmer, Rich↗
DOE OSTI2019

Input-output processing on a remote integrated circuit chip

An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.

42 ENGINEERING↗
DOE OSTI2021

Routing flits in a network-on-chip based on operating states of routers

A system is described that includes an integrated circuit chip having a network-on-chip. The network-on-chip includes multiple routers arranged in a topology and a separate communication link coupled between each router and each of one or more neighboring routers of that router among the multiple routers in the topology. The integrated circuit chip also includes multiple nodes, each node coupled to a router of the multiple routers. When operating, a given router of the multiple routers keeps a record of operating states of some or all of the multiple routers and corresponding communication links. The given router then routes flits to destination nodes via one or more other routers of the multiple routers based at least in part on the operating states of the some or all of the multiple routers and the corresponding communication links.

Bharadwaj, Srikant↗
DOE OSTI2023

Hardware-in-the-Loop Evaluation of Grid-Edge DER Chip Integration Into Next-Generation Smart Meters: Preprint

To facilitate the implementation of distributed energy resource management systems (DERMS), we propose to insert a grid-edge distributed energy resource (DER) chip hosting a DERMS algorithm into the next generation of smart meters. This will create a pathway for the wide adoption of DERMS technology because many utilities plan to invest in advanced metering infrastructure in the near future. This will also bridge the gap between an electrical power utility and DERs behind the meter. The DER chip is designed to follow power direction signals from the DERMS coordinator while balancing its local objectives. We tested the chip using a controller- and power-hardware-in-the-loop evaluation under three scenarios that a DERMS could face in the real world. The DER chip was capable of and effective at directing four heterogeneous DERs to respond to a DERMS coordinator for grid services (e.g., voltage regulation and a virtual power plant).

distributed energy resource management system↗
DOE OSTI2021

Three influential factors on colloidal nanoparticle deposition for heat conduction enhancement in 3D chip stacks

Thermal management is one of the major challenges facing the development of three-dimensional (3D) chip stacks. Recently, experimental studies have shown that neck-based thermal structure (NTS) between chip layers formed by drying of colloidal suspension in cavity filled with micro-size particles can improve the vertical heat conduction threefold. However, a deep understanding of the mechanisms of neck formation and its influence on heat conduction is still lacking. In this paper, we numerically study the effects of three parameters, i.e., initial nanoparticle concentration, drying temperature and chip surface wettability on neck formation between filler particles and on the resulting heat conduction of the NTS. With increasing nanoparticle concentration, the size and number of necks increase, resulting in an increased effective thermal conductivity (ETC) of NTS. The drying temperature is found to have only little influence on the ETC of resultant NTS, while the neck size and spatial distribution become more uniform at higher drying temperature. When reducing the wettability of the top and bottom surfaces of the cavity, the necks shrink in size until completing evacuating at the top and bottom layers, while the size of the necks between filler particles in the middle height of the cavity expands slowly. In consequence, the ETC of NTS drops at an increasing rate. Being able to reveal the underlying multiple mechanisms of two-phase flow, phase change and heat transport, the current numerical study suggests optimal values for the deposition process, with initial nanoparticle concentration over 0.8%, a drying temperature of 60°C and a uniform contact angle of 30° for practical production of NTS.

3D chip stacks↗
DOE OSTI2021

High-throughput and high-efficiency sample preparation for single-cell proteomics using a nested nanowell chip

Abstract Global quantification of protein abundances in single cells could provide direct information on cellular phenotypes and complement transcriptomics measurements. However, single-cell proteomics is still immature and confronts many technical challenges. Herein we describe a nested nanoPOTS (N2) chip to improve protein recovery, operation robustness, and processing throughput for isobaric-labeling-based scProteomics workflow. The N2 chip reduces reaction volume to <30 nL and increases capacity to >240 single cells on a single microchip. The tandem mass tag (TMT) pooling step is simplified by adding a microliter droplet on the nested nanowells to combine labeled single-cell samples. In the analysis of ~100 individual cells from three different cell lines, we demonstrate that the N2 chip-based scProteomics platform can robustly quantify ~1500 proteins and reveal membrane protein markers. Our analyses also reveal low protein abundance variations, suggesting the single-cell proteome profiles are highly stable for the cells cultured under identical conditions.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2020

On-Chip Single-Layer Integration of Diamond Spins with Microwave and Plasmonic Channels

On-chip scalable integration represents a major challenge for practical quantum devices. One particular challenge is to implement on-chip optical readout of spins in diamond. This readout requires simultaneous application of optical and microwave fields along with the efficient collection of fluorescence. These requirements are typically met using bulk optical components and dedicated microwave lines. Here, we experimentally demonstrate an on-chip integrated interface for diamond nitrogen vacancy (NV) spin-state preparation and readout, implemented in a planar single layer with only one patterning step. A nanodiamond with NV centers is positioned inside a v-groove waveguide milled in a thick gold film. The gold film carries the microwave control signal, while the v-groove acts as a fluorescence collector and, potentially, as an integrated pump filter. Hence, the device dimensions and fabrication complexity are substantially reduced. Our approach fosters further development of ultracompact nanoscale quantum sensors and quantum information processing devices on a monolithic platform.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

Chip-integrated metasurface full-Stokes polarimetric imaging sensor

Abstract Polarimetric imaging has a wide range of applications for uncovering features invisible to human eyes and conventional imaging sensors. Chip-integrated, fast, cost-effective, and accurate full-Stokes polarimetric imaging sensors are highly desirable in many applications, which, however, remain elusive due to fundamental material limitations. Here we present a chip-integrated Meta surface-based Full-Stokes Polar imetric Im aging sensor (MetaPolarIm) realized by integrating an ultrathin (~600 nm) metasurface polarization filter array (MPFA) onto a visible imaging sensor with CMOS compatible fabrication processes. The MPFA is featured with broadband dielectric-metal hybrid chiral metasurfaces and double-layer nanograting polarizers. This chip-integrated polarimetric imaging sensor enables single-shot full-Stokes imaging (speed limited by the CMOS imager) with the most compact form factor, records high measurement accuracy, dual-color operation (green and red) and a field of view up to 40 degrees. MetaPolarIm holds great promise to enable transformative applications in autonomous vision, industry inspection, space exploration, medical imaging and diagnosis.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Initial assessment of second generation of large-area picosecond photodetectors with multi-channel systems-on-a-chip readout

Here, we first briefly describe the history and motivation behind Cherenkov and scintillation light detection. We then discuss the instrumentation needed to detect these photons as it applies to both photodetectors and readout electronics. One of the motivations is future large neutrino detectors that could, in principle, differentiate between Cherenkov and scintillation light if using novel water-based scintillators. In this paper, we present the first measurements utilizing the second generation of Large Area Picosecond Photodetectors (LAPPDs) in conjunction with commercial system-on-a-chip readouts from Nalu Scientific—in particular, the High Density System on Chip (HDSoC) and Advanced ASoC Rapid Digitizer, Variable Adaptive Readout Chip (AARDVARC) platforms. These state-of-the-art full-waveform digitizers feature sampling rates on the order of 1 and 10 samples per nanosecond, respectively. Using a picosecond laser, we measured the timing jitter between a pair of LAPPD channels, demonstrating the potential of this setup for precise timing applications.

Li, V. A. [Lawrence Livermore National Laboratory ↗
DOE OSTI2024

GaN-based W-band receiver chip development for fusion plasma diagnostics

Millimeter-wave diagnostics have proven effective on various magnetic fusion devices worldwide, yet the formidable challenges posed by the harsh environments of future burning plasma devices, characterized by extreme temperatures, pressures, and radiation levels, remain a significant hurdle. To address these challenges, the utilization of wide bandgap Gallium Nitride (GaN)-based millimeter-wave diagnostics is a most promising solution for fusion reactor safety monitoring and control. A noteworthy W-band GaN-based system-on-chip receiver has been the demonstrated by employing HRL T3 40 nm GaN technology. This receiver chip, compactly designed with dimensions of 3 × 5 mm 2 , incorporates essential components such as the 75–110 GHz RF Low-Noise Amplifier (LNA), mixer, Intermediate Frequency (IF) amplifier, and Local Oscillator (LO) chain. This receiver chip will be packaged as a millimeter-wave receiver module and applied on the DIII-D National Fusion Facility, for fusion plasma edge shape monitoring for operational safety and dangerous disruption prediction. The laboratory measurement results have demonstrated suitable performance. Furthermore, this advancement is pivotal for accurate analysis of plasma behavior in the extreme conditions of burning plasma devices, driving progress in fusion research and technology.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗
DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2024

High power chip-scale laser

The lack of high-power integrated lasers has been limiting silicon photonics. Despite much progress in chip-scale laser integration, power output remains below levels required for key applications due to low energy efficiency at high pumping currents. Here we break this power limitation by coupling a broad-area multimode gain chip to a silicon-nitride ring resonator and single-mode filter. The resulting optical feedback causes the multimode-gain chip to concentrate its power into a single highly coherent mode. Our device produces more than 150 mW of power and 400 kHz linewidth. We achieve these metrics while maintaining a small footprint of 3 mm 2 .

Antman, Yair↗
DOE OSTI2023

A self-certifying FPGA based pixel readout chip test system for CMS ETL upgrade

A flexible self-certifying pixel readout test system for testing the Endcap Timing Read-Out Chip (ETROC) has been developed for the CMS MIP Timing Detector (MTD), part of the upgrade for the HL-LHC. The system includes an FPGA-based (Xilinx KC705) test system that can take data from an emulator or up to four ETROC boards in telescope mode. A python based DAQ system simplifies configuration, calibration, and testing of the chips. The system provides an efficient & reliable solution for testing ETROC (ETROC2 since April 2023 with 16x16 pixels, full-size, full functionality prototype) and can be extended to other readout chips with similar architecture (AIDA integration is currently being explored).

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

The Chocolate Chip Cookie Model: Dust Geometry of Milky Way–like Disk Galaxies

We present a new two-component dust geometry model, the Chocolate Chip Cookie model, where the clumpy nebular regions are embedded in a diffuse stellar/interstellar medium disk, like chocolate chips in a cookie. By approximating the binomial distribution of the clumpy nebular regions with a continuous Gaussian distribution and omitting the dust scattering effect, our model solves the dust attenuation process for both the emission lines and stellar continua via analytical approaches. Our Chocolate Chip Cookie model successfully fits the inclination dependence of both the effective dust reddening of the stellar components derived from stellar population synthesis and that of the emission lines characterized by the Balmer decrement for a large sample of Milky Way–like (MW-like) disk galaxies selected from the main galaxy sample of the Sloan Digital Sky Survey. Our model shows that the clumpy nebular disk is about 0.55 times thinner and 1.6 times larger than the stellar disk for MW-like galaxies, whereas each clumpy region has a typical optical depth of τ cl,V ~ 0.5 in the V band. After considering the aperture effect, our model prediction on the inclination dependence of dust attenuation is also consistent with observations. Not only that, in our model, the dust attenuation curve of the stellar population naturally depends on the inclination, and its median case is consistent with the classical Calzetti law. As the modeling constraints are from the optical wavelengths, our model is unaffected by the optically thick dust component, which however could bias the model's prediction of the infrared emissions.

79 ASTRONOMY AND ASTROPHYSICS↗