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At least 91 records · Page 5

Implementing machine learning methods on QICK hardware for qubit readout & control

Quantum readout and control is a fundamental aspect of quantum computing that requires accurate measurement of qubit states. Errors emerge in all stages, from initialization to readout, and identifying errors in post-processing necessitates resource-intensive statistical analysis. In our work, we use a lightweight fully-connected neural network (NN) to classify states of a transmon system with no prior processing. Our NN accelerator yields higher fidelities (92%) than the classical matched filter method (84%). By exploiting the natural parallelism of NNs and their placement near the source of data on field-programmable gate arrays (FPGAs), we can achieve ultra-low latency on the Quantum Instrumentation Control Kit (QICK). Integrating machine learning methods on QICK opens several pathways for efficient real-time processing of quantum circuits.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

An Integrated Framework for Memory-Centric Analysis: From Trace Collection to Co-Design

The memory wall phenomenon—where advances in processor performance significantly outpace those in memory subsystems—poses a fundamental challenge for contemporary computing systems. In memory-bound applications, memory subsystem behavior dominates performance, yet existing analysis approaches present significant limitations: detailed microarchitectural simulators require days to weeks to simulate modest workloads; hardware performance counters provide only aggregate statistics that obscure temporal and spatial access patterns; and scaled simulation approaches face challenges in capturing certain behaviors that emerge at larger scales. These limitations reflect a processor-centric design philosophy increasingly misaligned with memory-bound workloads where detailed understanding of memory access patterns, cache hierarchy interactions, and contention is critical for effective optimization. This paper presents an integrated framework for memory-centric analysis that enables effective hardware-software co-design. We describe practical trace collection techniques, including hardware-assisted processor tracing with minimal overhead and portable software-based instrumentation with statistical sampling. We present multi-perspective analysis methods that examine memory behavior from temporal, sequential, spatial, and relational viewpoints, revealing distinct optimization opportunities invisible in aggregate metrics. We detail an architectural modeling framework that uses sampled traces with temporal interpolation and confidence-based filtering to evaluate cache and memory configurations. Evaluation on representative benchmarks demonstrates that this framework achieves practical accuracy (L2 cache errors of 2.64\%, confidence-filtered L3 errors of 9.92\%, bandwidth errors of 7.33\%) while providing substantial speedup (26.8×) over cycle-accurate simulation, enabling rapid design space exploration. We demonstrate how this integrated framework enables systematic identification of both hardware optimizations (memory controller tuning, bank partitioning, NUMA configuration) and software optimizations (data layout restructuring, prefetching strategies, memory-aware scheduling). Through this comprehensive treatment of the memory-centric analysis pipeline—from trace collection through architectural modeling to co-design application—we provide researchers and practitioners with practical techniques for addressing memory bottlenecks in contemporary computing systems.

Gajaria, Dhruv Mayur↗

Leveraging National Laboratory Assets to Address Stability Challenges due to Declining Grid Inertia Using Geographically Distributed Electrical–Thermal Co-Emulation

Due to increased penetration of low-inertia resources into the electric grid, challenges are increasing for maintaining wide-area system stability. Grid stability assessment requires a faithful representation of the multiple-physics interaction at the system level, and timescales of interaction varying in orders of magnitude, from microseconds to seconds to several minutes. Along with the simulation-based techniques, hardware-in-the-loop (HIL), controller HIL, and power HIL techniques have been developed to better understand the emergent behavior of the system with emerging technologies. US National Laboratories have played a vital role in research and development to understand the behavior of individual technologies and devices integrated to the electric grid. Each national laboratory forwards a technological and strategic initiative tied core and enabling capabilities. Due to strategic, efficiency, and economic reasons, not all the labs have assets to conduct research on all technologies concomitantly, so it becomes crucial to integrate the labs across geographies to understand the interplay of different technologies together at the system level. This approach avoids duplication of the assets at different lab facilities and helps understand the integrated system behavior of various technologies representative of actual grid conditions by connecting multiple national labs. This article talks about techniques of connecting three national laboratories to enable co-emulation of electrical–mechanical–thermal characteristics of devices and systems. Such an approach can be used to understand the dynamic and transient interaction of multi-physics in a system level, at-scale emulation using real-time simulation tools and techniques.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Multi-purpose quantum laboratories from superconducting circuits

Superconducting circuits (SCs) are the cornerstone of modern quantum technology, enabling scalable computing through coherent control of macroscopic quantum states. Through a legacy that predates modern quantum computing, SCs have emerged as high-precision instruments for discovery. In this review, we highlight the role of SCs as general-purpose quantum laboratories, outlining the emerging landscape of correlated matter-circuit science. We review and unify the capabilities of superconducting quantum hardware across condensed matter, high energy and quantum information sciences. We trace the technical evolution of these architectures, illustrating how their foundational development has culminated in a toolkit for resolving the complexities of macroscopic quantum states.

Arora, Arpit [UCLA, Los Angeles (main); UCLA; Haim↗

Athena: High-Performance Sparse Tensor Contraction Sequence on Heterogeneous Memory

Sparse tensor contraction sequence has been widely employed in many fields, such as chemistry and physics. However, how to efficiently implement the sequence faces multiple challenges, such as redundant computations and memory operations, massive memory consumption, and inefficient utilization of hardware. To address the above challenges, we introduce Athena, a high-performance framework for SpTC sequences. Athena introduces new data structures, leverages emerging Optane-based heterogeneous memory (HM) architecture, and stage parallelism. In particular, Athena introduces shared hash table-represented sparse accumulator to eliminate unnecessary input processing and data migration; Athena uses a novel data-semantic guided dynamic migration solution to make the best use of the Optane-based HM for high performance; Athena also co-runs execution phases with different characteristics to enable high hardware utilization. Evaluating with 12 datasets, we show that Athena brings 327-7362× speedup over the state-of-the-art SpTC algorithm. With the dynamic data placement guided by data semantics, Athena brings performance improvement on Optane-based HM over a state-of-the-art software-based data management solution, a hardware-based data management solution, and PMM-only by 1.58×, 1.82×, and 2.34× respectively.

Liu, Jiawen↗

Metal additive manufacturing simulation across length, time, and computing scales

Metal additive manufacturing (AM) offers a unique opportunity for production of advanced materials and complex geometries. However, variability in microstructure and properties challenges conventional approaches to design, process optimization, qualification, and materials selection. Modeling and simulation can improve understanding of AM processing and materials, but also poses major challenges for existing computational methods. Simultaneously, modern scientific computing hardware has become increasingly complex, most notably with the adoption of hybrid architectures such as Graphical Processing Units (GPUs). If appropriately utilized, emerging computational capabilities provide an opportunity to reveal new insight into AM processing and the resulting material structure and properties. In this review we describe the computational AM landscape, identify critical gaps, and highlight opportunities to impact the development and application of AM. First, the requirements and challenges of representative AM problem statements will be defined. Here, these problems range from scientific studies to industrial applications and are designed to capture the breadth of challenges facing the AM community. Next, the current state of AM modeling and simulation is evaluated, broken down by enabling hardware and software, process simulation, microstructure simulation, and property simulation. Each section describes the diversity of simulation approaches and associated trade-offs in physical fidelity and computational expense. Each area is then assessed based on their suitability and readiness for current and developing computational architectures. Lastly, the greatest opportunities for future research and application are highlighted, including gaps in modeling capabilities, opportunities for near-term application, and key scientific challenges.

additive manufacturing↗

Radiation-Hardened GaN-Based Wireless Communications Architectures for Terrestrial Nuclear Reactor Sensing and Instrumentation

Wireless technologies have become increasingly common in applications, ranging from close proximity inductive communication links in medical devices to short-range Bluetooth and WiFi communications and longer-range cellular communications. Nonetheless, these technologies are unsuitable for use in or around nuclear reactors due to the extreme radiation and temperatures inherent in these environments and their associated significant degradative effects on electronics hardware. However, recent work in wide bandgap– based electronics has shown promise for gallium nitride (GaN) as an emerging technology for the realization of practical wireless communications systems for use in harsh environments. This report presents initial progress on the development of wireless communications architectures designed specifically for nuclear reactor application, based on inherently radiation-hardened (rad-hard) GaN technology. Prior work on rad-hard analog communications topologies is reviewed, and several digital modulation and encoding schemes that utilize GaN-based electronics devices are newly proposed for application in reactor environments. Continuous-time and discrete-time system simulations were performed, and results are presented for the preliminary transmitter and receiver designs, respectively. In addition, an overview of a software-defined radio testbed, designed for communications protocol development, is provided. Future work will focus on implementing candidate radiation-resistant wireless architectures using a research AlGaN/GaN high electron mobility transistor (HEMT) integrated circuit process, which is available at the Ohio State University, and irradiation studies will be carried out to assess the true potential of this technology for reactor application.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

Power Electronic Hardware-in-the-Loop (PE-HIL): Testing Individual Controllers in Large-Scale Power Electronics Systems

Large power electronics systems like multi-port autonomous reconfigurable solar power plant (MARS) are increasingly being researched upon to integrate emerging energy sources. MARS connects photovoltaic (PV) systems and energy storage systems (ESSs) to high-voltage direct current (HVdc) links/grids and high-voltage alternating current (ac) transmission grids. As these large power electronics systems incorporate complex hierarchical control systems that are close-by and communicate fast, the control systems require an unique power electronic hardware-in-the-loop (PE-HIL) real-time architecture to evaluate individual controllers. In this paper, a PE-HIL real-time architecture is proposed to evaluate one of the hundreds to thousands of digital signal processors (DSPs) that are a part of the complex hierarchical control system. The DSP connects to a central processing unit (CPU) and a field programmable gate array (FPGA) that form a part of the upper levels of the control system. The DSP is part of the lower level of the control system. The proposed PE-HIL architecture is tested and evaluated. Preliminary test results are presented to showcase the concept.

Debnath, Suman↗

Magnetic hysteresis experiments performed on quantum annealers

While quantum annealers have emerged as versatile and controllable platforms for experimenting on correlated spin systems, the important phenomenology of magnetic memory and hysteresis remain unexplored on hardware designed to escape metastable states via quantum tunneling. Here, we present the first general protocol to experiment on magnetic hysteresis on programmable quantum annealers and implement it on three D-Wave superconducting qubit quantum annealers, using up to thousands of spins, for both ferromagnetic and disordered Ising models, and across different graph topologies. We observe hysteresis loops whose area depends nonmonotonically on quantum fluctuations, exhibiting both expected and unexpected features, such as disorder-induced steps and nonmonotonicities. Our work establishes quantum annealers as a platform for probing nonequilibrium emergent magnetic phenomena, thereby broadening the role of analog quantum computers into foundational questions in condensed matter physics.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

A semi-agnostic ansatz with variable structure for variational quantum algorithms

Quantum machine learning—and specifically Variational Quantum Algorithms (VQAs)—offers a powerful, flexible paradigm for programming near-term quantum computers, with applications in chemistry, metrology, materials science, data science, and mathematics. Here, one trains an ansatz, in the form of a parameterized quantum circuit, to accomplish a task of interest. However, challenges have recently emerged suggesting that deep ansatzes are difficult to train, due to flat training landscapes caused by randomness or by hardware noise. This motivates our work, where we present a variable structure approach to build ansatzes for VQAs. Our approach, called VAns (Variable Ansatz), applies a set of rules to both grow and (crucially) remove quantum gates in an informed manner during the optimization. Consequently, VAns is ideally suited to mitigate trainability and noise-related issues by keeping the ansatz shallow. We employ VAns in the variational quantum eigensolver for condensed matter and quantum chemistry applications, in the quantum autoencoder for data compression and in unitary compilation problems showing successful results in all cases.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Training Spiking Neural Networks with Synaptic Plasticity under Integer Representation

Neuromorphic computing is emerging as a promising Beyond Moore computing paradigm that employs event-triggered computation and non-von Neumann hardware. Spike Timing Dependent Plasticity (STDP) is a well-known bio-inspired learning rule that relies on activities of locally connected neurons to adjust the weights of their respective synapses. In this work, we analyze a basic STDP rule and its sensitivity on the different hyperparameters for training spiking neural networks (SNNs) with supervision, customized for a neuromorphic hardware implementation with integer weights. We compare the classification performance on four UCI datasets (iris, wine, breast cancer and digits) that depict varying levels of complexity. We perform a search for optimal set of hyperparameters using both grid search and Bayesian optimization. Through the use of Bayesian optimization, we show the general trends in hyperparameter sensitivity in SNN classification problem. With the best sets of hyperparameters, we achieve accuracies comparable to some of the best performing SNNs on these four datasets. With a highly optimized supervised STDP rule we show that these accuracies can be achieved with just 20 epochs of training.

Kulkarni, Shruti↗

The potential of quantum annealing for rapid solution structure identification

Abstract The recent emergence of novel computational devices, such as quantum computers, coherent Ising machines, and digital annealers presents new opportunities for hardware-accelerated hybrid optimization algorithms. Unfortunately, demonstrations of unquestionable performance gains leveraging novel hardware platforms have faced significant obstacles. One key challenge is understanding the algorithmic properties that distinguish such devices from established optimization approaches. Through the careful design of contrived optimization tasks, this work provides new insights into the computation properties of quantum annealing and suggests that this model has the potential to quickly identify the structure of high-quality solutions. A meticulous comparison to a variety of algorithms spanning both complete and local search suggests that quantum annealing’s performance on the proposed optimization tasks is distinct. This result provides new insights into the time scales and types of optimization problems where quantum annealing has the potential to provide notable performance gains over established optimization algorithms and suggests the development of hybrid algorithms that combine the best features of quantum annealing and state-of-the-art classical approaches.

97 MATHEMATICS AND COMPUTING↗

A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs

In the last decade, Artificial Intelligence (AI) through Deep Neural Networks (DNNs) has penetrated virtually every aspect of science, technology, and business. Many types of DNNs have been and continue to be developed, including Convolutional Neural Networks (CNNs), Recurrent Neural Net- works (RNNs), and Graph Neural Networks (GNNs). The overall problem for all of these Neural Networks (NNs) is that their target applications generally pose stringent constraints on latency and throughput, while also having strict accuracy requirements. There have been many previous efforts in creating hardware to accelerate NNs. The problem designers face is that optimal NN models typically have significant irregularities, making them hardware-unfriendly. In this paper, we first define the problems in NN acceleration by characterizing common irregularities in NN processing into 4 types; then we summarize the existing works that handle the four types of irregularities efficiently using hardware, especially FPGAs; finally, we provide a new vision of next-generation FPGA-based NN acceleration: that the emerging heterogeneity in the next-generation FPGAs is the key to achieving higher performance.

Geng, Tong↗

Addressing Rising Energy Demand Through Innovation

The U.S. is facing a significant increase in energy demand, driven by AI advancements, the rapid expansion of data centers, manufacturing and industrial growth, and the electrification of transportation and buildings. Buildings alone account for approximately 75% of U.S. electricity consumption and 40% of total energy use. To address these challenges, NLR leverages its state-of-the-art research facilities, advanced energy modeling, hardware-in-the-loop emulation, and real-world demonstrations to provide data-driven insights that de-risk emerging energy solutions, increase efficiency and demand flexibility, optimize grid controls, and identify vulnerabilities to enhance energy security. This presentation will highlight our research ecosystem and its role in supporting a more reliable, affordable, and adaptive energy infrastructure in the face of accelerating demand.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Efficient Probabilistic Computing with Stochastic Perovskite Nickelates

Probabilistic computing has emerged as a viable approach to solve hard optimization problems. Devices with inherent stochasticity can greatly simplify their implementation in electronic hardware. In this report we demonstrate intrinsic stochastic resistance switching controlled via electric fields in perovskite nickelates doped with hydrogen. The ability of hydrogen ions to reside in various metastable configurations in the lattice leads to a distribution of transport gaps. With experimentally characterized p-bits, a shared-synapse p-bit architecture demonstrates highly parallelized and energy-efficient solutions to optimization problems such as integer factorization and Boolean satisfiability. The results introduce perovskite nickelates as scalable potential candidates for probabilistic computing and showcase the potential of light-element dopants in next-generation correlated semiconductors.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks

Deep neural network (DNN) models are being expanded to a broader range of applications. The computational capability of traditional hardware platforms cannot accommodate the growth of model complexity. Among recent technologies to accelerate DNN, resistive memory (ReRAM)-based processing-in-memory (PIM) emerged as a promising solution for DNN inference due to its high efficiency for matrix-based computation. We face two major technical challenges in extending the use of ReRAM-based accelerators for training: (1) full-precision data is essential in back-propagation; (2) the need to support both feed-forward and back-propagation aggravates the data-movement burden. We propose a heterogeneous architecture named as 3D-ReG, which leverages full-precision GPU to ensure training accuracy and low-overhead 3D integration to provide low-cost data movements. Moreover, we introduce conservative and aggressive task-mapping schemes, which partition the computation phases in different ways to balance execution efficiency and training accuracy. We evaluate 3D-ReG implemented with two 3D integration technologies, through-silicon vias (TSVs) and monolithic inter-tier vias (MIVs), and compare them with GPU-only and PIM-only counterparts. Various GPU-only platforms using two main-memory technologies (DRAM, ReRAM) and three interconnect technologies (2D, TSV, MIV) are evaluated as well. Experimental results show that 3D-ReG can achieve on average 5.64× training speedup and 3.56× higher energy efficiency compared with the GPU with DRAM as main memory, at the cost of 0.05%–3.39% accuracy drop. We define a new metric, gain-loss ratio (GLR), which quantitatively evaluates the capability of a DNN training hardware in terms of the model accuracy and hardware efficiency. The results of our comparison show that the aggressive task-mapping scheme on MIV-based 3D-ReG outperforms the other methods.

Computer Science↗

Collaborative Research: Improved Efficiency and Coupling of the Radiation Code in the ACME Earth System Model. Final Report

This final report details all work performed on the project by both project partners. This project provided support to properly couple RTE+RRTMGP, a high-performance broadband radiation code, within DOE’s Energy Exascale Earth System Model (E3SM). RTE+RRTMGP is a successor to the RRTMG radiation code, which has been widely accepted for its speed and accuracy by the global modeling community, and has been in use in the NCAR CESM for many years and was implemented in the initial version of E3SM. However, the computational cost of RRTMG remains high relative to other components in part due to its complexity and to its inefficient use of modern optimization strategies, issues that were rectified by the development of RTE+RRTMGP. Many of the accomplishment in this project necessitated significant collaboration with the E3SM development team. One focus of the project was to enhance the code’s optimization on the limited number of emerging computing systems on which the model is expected be used, including Many Integrated Core (MIC) architectures and Graphics Processing Unit (GPU) hardware. We also developed additional capabilities for RTE+RRTMGP that E3SM scientists identified as important for the planned applications of the model. The result of our project was optimization of a key physical component (radiative transfer calculations) of E3SM, directly supporting E3SM’s overarching global modeling objectives. More broadly, this project provided overall advancements in the use of radiative transfer calculations in atmospheric modeling and simulation, particularly for climate.

54 ENVIRONMENTAL SCIENCES↗

Logic in Memory Emulator

Logic in Memory Emulator (LiME) is a hardware/software tool specially designed for memory system evaluation and experiment. Emerging memories display a wide range of bandwidths, latencies, and capacities, making it challenging for the computer architect to navigate the design space of potential memory configurations, and for the application developer to assess performance implications of using such memories. With the LiME framework, architectural ideas can be prototyped in great detail yet with sufficient performance to support realistic evaluation on long running applications. LiME consists of two fundamental components: 1) the hardware and OS infrastructure for the emulator, and 2) a suite of benchmark applications to assist in characterizing the performance of current and future computer architectures. Some of the applications have been collected from other open source projects. Uses: Logging, replay and analysis of an application's memory behavior Evaluate impact of emerging memory technology on application performance. Emulate complex memory interactions in whole applications orders of magnitude faster than software simulation. Emulate acceleration hardware co-located with the memory subsystem. Features: Capture and log external memory accesses to a separate off-chip memory device without affecting application execution. Memory traces include the address, length, timestamp, and optionally the data for each transaction. Captured trace data can be saved to an SD card for off-line analysis. Configure a wide range of memory latencies in sub-nanosecond increments that encompass highbandwidth and storage class memories. Specify regions of interest (ROI) in applications to reduce the amount of trace data captured for analysis. Currently supports execution on Xilinx Zynq SoC which integrates an ARM processor with FPGA logic on a single device. Applications can be run under Linux or in bare metal mode on the ARM cores.

Jain, AbhishekK↗