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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Advanced Photovoltaic Inverter Control Development and Validation in a Controller-Hardware-in-the-Loop Test Bed

Penetration of solar photovoltaic (PV) installations into the grid has increased in recent years. In the past, photovoltaic installations have not included grid-support functionality. Grid support functions including Volt-VAR (VVAR), Frequency-Watt (FW), Volt-Watt (VW), frequency/voltage-ride through, as well as other inverter functions such as anti-islanding are recommended by standards such as IEEE 1547 to allow PV inverters to contribute to acceptable operation and stability of distribution systems with high penetrations of PV and to ensure predictable response of the PV inverters. First, low-level and high-level grid support inverter control functions were developed and tested in simulation. The developed controller is able to integrate advanced controller functions in a coordinated approach, avoiding any conflict between the different control objectives. The algorithms were then programmed on an off-the-shelf embedded controller that included a dual-core CPU and FPGA. The details of the high-level grid support function and the lower level switching control will be presented. Second, this programmed controller is tested using a controller-hardware-in-the-loop (CHIL) test bed setup using an FPGA-based real-time simulator. The CHIL setup has the capability to run at a 500 nano-second time-step to accommodate the 20 kHz switching frequency of the developed controller. The advanced control function and CHIL test bed details provided here will aide future researchers to design, implement, and test advanced inverter functions for PV inverters.

14 SOLAR ENERGY↗
DOE OSTI2022

Power Electronic Hardware-in-the-Loop (PE-HIL): Testing Individual Controllers in Large-Scale Power Electronics Systems

Large power electronics systems like multi-port autonomous reconfigurable solar power plant (MARS) are increasingly being researched upon to integrate emerging energy sources. MARS connects photovoltaic (PV) systems and energy storage systems (ESSs) to high-voltage direct current (HVdc) links/grids and high-voltage alternating current (ac) transmission grids. As these large power electronics systems incorporate complex hierarchical control systems that are close-by and communicate fast, the control systems require an unique power electronic hardware-in-the-loop (PE-HIL) real-time architecture to evaluate individual controllers. In this paper, a PE-HIL real-time architecture is proposed to evaluate one of the hundreds to thousands of digital signal processors (DSPs) that are a part of the complex hierarchical control system. The DSP connects to a central processing unit (CPU) and a field programmable gate array (FPGA) that form a part of the upper levels of the control system. The DSP is part of the lower level of the control system. The proposed PE-HIL architecture is tested and evaluated. Preliminary test results are presented to showcase the concept.

Debnath, Suman↗
DOE OSTI2023

Machine Learning Models for Network Traffic Classification in Programmable Logic

Network traffic classification via machine learning on network packet payloads has emerged as an active area of research for network security due to the high accuracy machine learning models have achieved in classifying payloads. For effective deployment as part of network security, these machine learning models must not only classify malicious packet payloads accurately, they must also identify anomalous payloads and perform inference at speeds generally faster than 10,000 packets per second to be effective. This work explores the in- ference speeds and accuracy of several neural network models implemented in programmable logic on various field programmable gate arrays (FPGA) including the Xilinx VC1902 and Xilinx Zynq Ultrascale+. This work also presents the design and performance of both an autoencoder and variational autoencoder programmed on the FPGA for identifying anomalous packet payloads. The performance benefits of the FPGA implementation for this type of packet payload inspection driven by machine learning are compared against graphics processing unit (GPU) inference implementations run on two state-of-the-art datacenter GPU devices, the NVIDIA V100 and A100. The model accuracy difference between the FPGA and GPU implementations was found to be 4% or less while the Xilinx VC1902 outperformed both the NVIDIA V100 and A100 for inference speeds on all the models explored except the variational autoencoder.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Two-Layer Predictive Controller for V2G and G2V Services Using on Wireless Power Transfer Technology

This paper presents a comprehensive solution that allows electric vehicles (EV) to autonomously charge and discharge their batteries wirelessly during long term parking and/or the transient stops. A two-layer power-flow controller for bidirectional wireless power transfer system (BWPTS) in EVs applications is proposed. The proposed controller can manage the bidirectional power-flow between EV and surrounding infrastructures such as power grid, home microgrid, building micro-grid, road or another vehicle. It consists of two levels of control; the first is responsible for communicating with the surrounding infrastructures and gathering information from driver, charging station, power grid and battery management system and then, based on these information, it estimates the EV's psychological price as a function of its battery's state-of-charge (SOC) and compares it with the energy price to decide whether to charge, discharge or abstain, and how much the charging or discharging rate. The second layer receives the reference signal from the first one and generates the control parameters for two synchronized resonant converters (one is on the vehicle side and the other is on the grid side) to provide the requited power-flow. The proposed controller is adaptively estimating the system parameters to consider the misalignment conditions effects on the system performance. The parameter estimation is achieved using only one voltage sensor. The second layer control is designed based on a new analytical modeling for the power flow in the system. For verification purposes, a prototype for BWPTS was built and driven by the proposed controller, which was implemented using a field-programmable gate array (FPGA) integrated circuit. The proposed controller provides very fast and stable response during both the transient and steady state operation in comparison with the conventional PI controller.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2024

Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering

Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training method, we generate compact SNN models with 91% signal efficiency, akin to convolutional neural networks but with half the parameters. However, deploying near the detector poses a challenge because the SNN must handle a sustained input data rate exceeding 1013 GB/s. To overcome this, we propose a novel hardware architecture that uses high-level synthesis to construct a tuned architecture for the EONS-trained SNN. In addition to the analysis and validation with an AMD Xilinx Artix-A7 FPGA, our solution consumes only ç24% of FPGA LUT and flipflops. We also introduce an innovative quantization method that reduces FPGA resource utilization by ç15% without compromising accuracy. Our FPGA implementation achieves computing latency of ç10 ns for smart-pixel application inference on an edge FPGA.

Miniskar, Narasinga Rao↗
DOE OSTI2017

Noise Radar Approach for Interrogating SAW Sensors Using Software Defined Radio

Passive, wireless surface acoustic wave (SAW) sensor systems can be approached from a radar perspective, where the SAW device is thought of as a cooperative target. Here, this paper investigates the use of a commercial-off-the-shelf software defined radio to interrogate wireless SAW sensors with a randomly generated interrogation pulse. The USRP B200mini is utilized as the transceiver platform with custom field-programmable gate array (FPGA) modifications to generate the random interrogation waveform and provide synchronization and buffering to the received signal. Each transmit sample bit in the FPGA is fed by an independent linear-feedback shift register, which generates pseudo-random I and Q samples for the interrogation pulse. An RF daughterboard has also been developed and integrated with the B200mini to increase the transmit power, provide filtering of the RF signals, and switch a signal antenna between the transmit and receive channels. Radio control and matched filter correlator post-processing are accomplished using Python. Design and implementation details for the FPGA modifications, RF daughterboard, and post-processing are discussed. Lastly, the system is demonstrated by wirelessly interrogating SAW temperature sensors at 915 MHz.

47 OTHER INSTRUMENTATION↗
DOE OSTI2018

Comparison of Doubly-Fed Induction Generator Machine Models for Real-Time Simulations

This work presents a detailed comparison among three implementations of the Doubly-Fed Induction Generator (DFIG) machine model. The alpha-beta-gamma, synchronous (dqo), and natural frame dynamic machine models were deployed on a Field-Programmable Gate Array (FPGA) and compared in terms of execution time and resource utilization. These machine models were also validated against a physical DFIG machine during balanced and unbalanced grid conditions. A benchmark is presented with the objective of selecting the machine model, orientation and state-space representation that is best suited for real-time simulations. The selected machine model is used to develop a real-time emulator of a Type-3 wind system. This emulator enables the study of wind turbine system in realtime using a validated platform while allowing controller testing without relying on expensive third-party solutions.

Ferrari Maglia, Max↗
DOE OSTI2020

IEEE 1547-2018 Based Interoperable PV Inverter with Advanced Grid-Support Functions

Grid integration of photovoltaic (PV) inverters has been increasing in the past decade. As a result of the uncertainties introduced with high penetrations of PV, better monitoring and control of the PV inverters becomes crucial for improving overall system stability. This paper focuses on the communications capability of the inverter controller and on enabling interoperability. Multiple standards are available to enable interoperability in PV inverters. In this paper, an interoperable controller, enabled by Distributed Network Protocol 3 (DNP3) communications protocols, is developed for a grid-connected, three-phase PV inverter. The DNP3 server for the PV inverter is programmed on the real-time layer of the field-programmable gate array (FPGA)-based inverter controller. Set points for advanced inverter control functions, such as volt/VAr curves, ride-through curves, are sent from a DNP3 client, a simulated distribution management system application, to the PV inverter through DNP3. This communications capability of the inverter controller is validated using a controller-hardware-in-the-loop experimental setup. The code developed to achieve the interoperability is available in the public domain through open-source software licensing. This interoperability will enable smoother grid integration of smart PV inverters with advanced grid-support functions as well as allow better monitoring and control of PV inverters for grid stability.

14 SOLAR ENERGY↗
DOE OSTI2016

Development of ROACH firmware for microwave multiplexed X-ray TES microcalorimeters

We are developing room temperature electronics based upon the ROACH platform for reading out microwave multiplexed X-ray TES. ROACH is an open-source hardware and software platform featuring a large Xilinx Field Programmable Gate Array (FPGA), Power PC processor, several 10GB Ethernet SFP+ interfaces, and a collection of daughter boards for analog signal generation and acquisition. The combination of a ROACH board, ADC/DAC conversion daughter boards, and hardware for RF mixing allows for the generation and capture of multiple RF tones for reading out microwave multiplexed x-ray TES microcalorimeters. The FPGA is used to generate multiple tones in base band, from 10MHz to 250MHz, which are subsequently mixed to RF in the multiple GHz range and sent through the microwave multiplexer. The tones are generated in the FPGA by storing a large lookup table in Quad Data Rate (QDR) SRAM modules and playing out the waveform to a DAC board. Once the signal has been modulated to RF, passed through the microwave multiplexer, and has been modulated back to base band, the signal is digitized by an ADC board. The tones are modulated to 0Hz by using a FPGA circuit consisting of a polyphase filter bank, several Xilinx FFT blocks, Xilinx CORDIC blocks (for converting to magnitude and phase), and special phase accumulator circuit for mixing to exactly 0Hz. Upwards of 256 channels can be simultaneously captured and written into a bank of 256 First-In-First-Out (FIFO) memories, with each FIFO corresponding to a channel. Individual channel data can be further processed in the FPGA before being streamed through a 10GB Ethernet fiber-optic interface to a Linux system. The Linux system runs software written in Python and QT C++ for controlling the ROACH system, capturing data, and processing data.

Firmware↗
DOE OSTI2019

FELIX-Based Readout of the Single-Phase ProtoDUNE Detector

Large liquid argon (LAr) time projection chambers (TPCs) have been adopted for the Deep Underground Neutrino Experiment (DUNE) experiment's far detector, which will be composed of four 17-kton detectors situated 1.5 km underground at the Sanford Underground Research Facility. This represents a large increase in scale compared to existing experiments. Both single- and dual-phase technologies will be validated at CERN, in cryostats capable of accommodating full-size detector modules, and exposed to low-energy charged particle beams. This program, called ProtoDUNE, also allows for extensive tests of data acquisition strategies. The Front-End LInk eXchange (FELIX) readout system was initially developed within the ATLAS collaboration and is based on custom field-programmable gate array (FPGA)-based Peripheral Component Interconnect Express input/output cards, connected through point-to-point links to the detector front end and hosted in commodity servers. FELIX will be used in the single-phase ProtoDUNE setup to read the data coming from 2560 anode wires organized in a single anode plane assembly (APS) structure. With a continuous readout at a sampling rate of 2 MHz, the system must deal with an input rate of 96 Gb/s. An external trigger will preselect time windows of 5 ms with interesting activity expected inside the detector. Event building will occur for triggered events, at a target rate of 25 Hz; the readout system will form fragments from the data samples matching the time window, carry out lossless compression, and forward the data to event building nodes over 10-Gb/s Ethernet. This paper discusses the design and implementation of this readout system as well as the first operational experience.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Real-Time Ethernet Interface for NSTX-U’s Thomson Scattering Diagnostic (2023)

Here, the multipoint Thomson scattering (MPTS) diagnostic system at the National Spherical Torus Experiment Upgrade (NSTX-U) facility is undergoing an upgrade to operate in real-time and interface with the plasma control system (PCS) for NSTX-U. Previous prototyping efforts have shown that spectral analysis and rapid calculations of electron temperature and density are possible on a real-time Linux machine when using up to a 100-Hz laser pulse repetition rate. A remaining challenge was transferring the real-time data to NSTX-U’s PCS, which utilizes the front panel data port (FPDP) protocol. The original proposed method was to convert the real-time data into analog values, but a new solution was developed to keep the output format digital by using an Ethernet controller with a field-programmable gate array (FPGA). This article focuses on a new input module that has been developed to accept incoming user datagram protocol (UDP) packets sent over Ethernet, convert into FPDP format, and integrate into the existing data stream under NSTX-U’s real-time framework.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Readout system of TPC/MPD NICA project

The time-projection chamber (TPC) is the main tracking detector in the MPD/NICA. The information on charge-particle tracks in the TPC is registered by the MWPG with cathode pad readout. The frontend electronics (FEE) are developed with use of modern technologies such as application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), and data transfer to a concentrator via a fast optical interface. The main parameters of the FEE are as follows: total number of channels, ∼95 000; data stream from the whole TPC, 5 GB/s; low power consumption, less than 100 mW/ch; signal to noise ratio (S/N), 30; equivalent noise charge (ENC), <1000e{sup –} (C{sub in} = 10–20 pF); and zero suppression (pad signal rejection ∼90%). The article presents the status of the readout chamber construction and the data acquisition system. The results of testing FEE prototypes are presented.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2016

IonControl v. 1.0

The IonControl software is a set of python scripts and Field-Programmable-Gate-Array (FPGA) code designed to control a trapped ion research experiment. It enables one to generate the pulses (time resolution: 20ns) necessary to control the quantum states of trapped ions and allows one to collect and analyze measurement results from trapped ion systems.

Maunz, Peter↗
DOE OSTI2021

LBNL BPM Firmware (CAL-BPM) v1.0

CAL-BPM is the firmware code base of the Advanced Light Source (ALS) Beam Position Monitor (BPM) Field Programmable Gate Array (FPGA) based electronics.

Norum, William↗
DOE OSTI2023

Quantum Instrumentation Control Kit Defect Arbitrary Waveform Generator (QICKDAWG) v.0

SAND2024-08598O The Quantum Instrumentation Control Kit Defect Arbitrary Waveform Generator (QICKDAWG) characterizes nitrogen-vacancy centers in diamond and other defects. It does this by using a radio frequency system-on-a-chip (RFSoC) field programmable gate array (FPGA). QICKDAWG synthesizes microwave pulses from the RFSoC to change the spin state of the defects. The software also allows for laser control using the RFSoC, which optically pumps defects. Ultimately, QICKDAWG supports the implementation of RFSoC FPGAs in defect characterization. This replaces the slow, expensive, traditional hardware, thus lowering the cost and time for defect characterization. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

SciDAC↗
DOE OSTI2024

Sentinel

Network intrusion detection systems (NIDS) are commonplace in network security but they frequently employ algorithms that are computational demanding requiring hardware and software with significant power requirements. Two examples of such resource-intensive algorithms used for network security are regular expression matching and broader signature pattern matching which are commonly used in deep packet inspection (DPI). Network security algorithms that have large power requirements may be a challenge for low-power internet-of-things (IoT) environments, which generally lack the power resources to implement complex security measures like computationally expensive DPI at the edge. Furthermore, IoT environments incorporating 5G standalone networks have network latency constraints beyond just power that make DPI at the edge even more difficult. Programmable logic is ideally suited for machine learning inference for DPI because of its deep instruction level parallelism and single-cycle memory access. Machine learning approaches for DPI have been explored before using the programmable logic of field programmable gate arrays (FPGA) as a potential solution for NIDS approaches that would be power-suitable for IoT. However, those previous programmable logic NIDS approaches utilize either a supervised or unsupervised learning model. Sentinel utilizes the ensemble of these two machine learning approaches known as a semi-supervised approach which has shown promise in NIDS implementations. Sentinel provides a programmable logic implementation of a semi-supervised approach for DPI which operates at much lower power and latency than a GPU implementation with negligible loss of accuracy due to quantization through a logistic regressor.

Anderson, MatthewW [Idaho National Laboratory (INL↗
DOE OSTI2014

Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays (September 2014 Milestone Report)

This is a report of the activities involving Task 2 of the NEET 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays. Using the analog blocks available in our currently pre-configured Via-Configured Array (VCA), we will perform a detailed schematic design of our system to include the signal-processing blocks for temperature, radiation and pressure. Control and data acquisition will be implemented with the Spartan-6 Field-Programmable Gate Array (FPGA) as well as wired serial communications with a remote computer to be used with this project. In addition, batteries and associated voltage regulators will be selected for powering the system. Fabrication may include a polyimide, printed circuit board (PCB) for improved radiation and temperature tolerance. The PCB will go through a layout process by one of the organizations we utilize for this function and be fabricated by another external vendor. Population of the system board will be performed using one of our in-house technicians or an outside vendor we commonly use. Five prototype systems (sensors, electronics board, battery power supply, and personal computer (PC) serial communications port) will be constructed to support the testing objectives of this work. Quality assurance will be performed at each step by both the submitters and the vendors.

36 MATERIALS SCIENCE↗