SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Micro Channel/Multibus-II interface circuit provides electrical interconnections enabling communications between Micro Channels of IBM Personal System/2 computers and IEEE 1296 standard Multibus-II parallel system bus (iPSB). Made mostly of commercially available parts, interface enables independent Micro Channels to communicate over iPSB without modification.
Earlier studies show that future human explorations missions are composed of multi-vehicle assemblies with interconnected electric power systems. Some vehicles are often intended to serve as flexible multi-purpose or multi-mission platforms. This drives the need for power architectures that can be reconfigured to support this level of flexibility. Power system developmental costs can be reduced, program wide, by utilizing a common set of modular building blocks. Further, there are mission operational and logistics cost benefits of using a common set of modular spares. These benefits are the goals of the Advanced Exploration Systems (AES) Modular Power System (AMPS) project. A common set of modular blocks requires a substantial level of standardization in terms of the Electrical, Data System, and Mechanical interfaces. The AMPS project is developing a set of proposed interface standards that will provide useful guidance for modular hardware developers but not needlessly constrain technology options, or limit future growth in capability. In 2015 the AMPS project focused on standardizing the interfaces between the elements of spacecraft power distribution and energy storage. The development of the modular power standard starts with establishing mission assumptions and ground rules to define design application space. The standards are defined in terms of AMPS objectives including Commonality, Reliability-Availability, Flexibility-Configurability and Supportability-Reusability. The proposed standards are aimed at assembly and sub-assembly level building blocks. AMPS plans to adopt existing standards for spacecraft command and data, software, network interfaces, and electrical power interfaces where applicable. Other standards including structural encapsulation, heat transfer, and fluid transfer, are governed by launch and spacecraft environments and bound by practical limitations of weight and volume. Developing these mechanical interface standards is more difficult but an essential part of defining physical building blocks of modular power. This presentation describes the AMPS projects progress towards standardized modular power interfaces.
A method and apparatus for detecting human eye defects, particularly detection of refractive error is presented. Eye reflex is recorded on color film when the eyes are exposed to a flash of light. The photographs are compared with predetermined standards to detect eye defects. The base structure of the ocular screening system is a folding interconnect structure, comprising hinged sections. Attached to one end of the structure is a head positioning station which comprises vertical support, a head positioning bracket having one end attached to the top of the support, and two head positioning lamps to verify precise head positioning. At the opposite end of the interconnect structure is a camera station with camera, electronic flash unit, and blinking fixation lamp, for photographing the eyes of persons being evaluated.
The Open Systems Interconnection (OSI) protocol suite is a result of a world-wide effort to develop international standards for networking. OSI is formalized through the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC). The goal of OSI is to provide interoperability between network products without relying on one particular vendor, and to do so on a multinational basis. The National Institute for Standards and Technology (NIST) has developed a Government OSI Profile (GOSIP) that specified a subset of the OSI protocols as a Federal Information Processing Standard (FIPS 146). GOSIP compatibility has been adopted as the direction for all U.S. government networks. OSI is extremely diverse, and therefore adherence to a profile will facilitate interoperability within OSI networks. All major computer vendors have indicated current or future support of GOSIP-compliant OSI protocols in their products. The NASA Science Internet (NSI) is an operational network, serving user requirements under NASA's Office of Space Science and Applications. NSI consists of the Space Physics Analysis Network (SPAN) that uses the DECnet protocols and the NASA Science Network (NSN) that uses TCP/IP protocols. The NSI Project Office is currently working on an OSI integration analysis and strategy. A long-term goal is to integrate SPAN and NSN into one unified network service, using a full OSI protocol suite, which will support the OSSA user community.
In recent years, some remote-sensing applications require advanced airborne multi-sensor systems to provide high performance reflective and emissive spectral imaging measurement rapidly over large areas. The key or unique problem of characteristics is associated with a black box back-end system that operates a suite of cutting-edge imaging sensors to collect simultaneously the high throughput reflective and emissive spectral imaging data with precision georeference. This back-end system needs to be portable, easy-to-use, and reliable with advanced onboard processing. The innovation of the black box backend is a miniaturized airborne imaging central server system (MAICSS). MAICSS integrates a complex embedded system of systems with dedicated power and signal electronic circuits inside to serve a suite of configurable cutting-edge electro- optical (EO), long-wave infrared (LWIR), and medium-wave infrared (MWIR) cameras, a hyperspectral imaging scanner, and a GPS and inertial measurement unit (IMU) for atmospheric and surface remote sensing. Its compatible sensor packages include NASA s 1,024 1,024 pixel LWIR quantum well infrared photodetector (QWIP) imager; a 60.5 megapixel BuckEye EO camera; and a fast (e.g. 200+ scanlines/s) and wide swath-width (e.g., 1,920+ pixels) CCD/InGaAs imager-based visible/near infrared reflectance (VNIR) and shortwave infrared (SWIR) imaging spectrometer. MAICSS records continuous precision georeferenced and time-tagged multisensor throughputs to mass storage devices at a high aggregate rate, typically 60 MB/s for its LWIR/EO payload. MAICSS is a complete stand-alone imaging server instrument with an easy-to-use software package for either autonomous data collection or interactive airborne operation. Advanced multisensor data acquisition and onboard processing software features have been implemented for MAICSS. With the onboard processing for real time image development, correction, histogram-equalization, compression, georeference, and data organization, fast aerial imaging applications, including the real time LWIR image mosaic for Google Earth, have been realized for NASA fs LWIR QWIP instrument. MAICSS is a significant improvement and miniaturization of current multisensor technologies. Structurally, it has a complete modular and solid-state design. Without rotating hard drives and other moving parts, it is operational at high altitudes and survivable in high-vibration environments. It is assembled from a suite of miniaturized, precision-machined, standardized, and stackable interchangeable embedded instrument modules. These stackable modules can be bolted together with the interconnection wires inside for the maximal simplicity and portability. Multiple modules are electronically interconnected as stacked. Alternatively, these dedicated modules can be flexibly distributed to fit the space constraints of a flying vehicle. As a flexibly configurable system, MAICSS can be tailored to interface a variety of multisensor packages. For example, with a 1,024x1,024 pixel LWIR and a 8,984x6,732 pixel EO payload, the complete MAICSS volume is approximately 7x9x11 in. (=18x23x28 cm), with a weight of 25 lb (=11.4 kg).
The high-speed ring bus at the Jet Propulsion Laboratory (JPL) allows for future growth trends in spacecraft seen with future scientific missions. This innovation constitutes an enhancement of the 1393 bus as documented in the Institute of Electrical and Electronics Engineers (IEEE) 1393-1999 standard for a spaceborne fiber-optic data bus. It allows for high-bandwidth and time synchronization of all nodes on the ring. The JPL ring bus allows for interconnection of active units with autonomous operation and increased fault handling at high bandwidths. It minimizes the flight software interface with an intelligent physical layer design that has few states to manage as well as simplified testability. The design will soon be documented in the AS-1393 standard (Serial Hi-Rel Ring Network for Aerospace Applications). The framework is designed for "Class A" spacecraft operation and provides redundant data paths. It is based on "fault containment regions" and "redundant functional regions (RFR)" and has a method for allocating cables that completely supports the redundancy in spacecraft design, allowing for a complete RFR to fail. This design reduces the mass of the bus by incorporating both the Control Unit and the Data Unit in the same hardware. The standard uses ATM (asynchronous transfer mode) packets, standardized by ITU-T, ANSI, ETSI, and the ATM Forum. The IEEE-1393 standard uses the UNI form of the packet and provides no protection for the data portion of the cell. The JPL design adds optional formatting to this data portion. This design extends fault protection beyond that of the interconnect. This includes adding protection to the data portion that is contained within the Bus Interface Units (BIUs) and by adding to the signal interface between the Data Host and the JPL 1393 Ring Bus. Data transfer on the ring bus does not involve a master or initiator. Following bus protocol, any BIU may transmit data on the ring whenever it has data received from its host. There is no centralized arbitration or bus granting. The JPL design provides for autonomous synchronization of the nodes on the ring bus. An address-synchronous latency adjust buffer (LAB) has been designed that cannot get out of synchronization and needs no external input. Also, a priority-driven cable selection behavior has been programmed into each unit on the ring bus. This makes the bus able to connect itself up, according to a maximum redundancy priority system, without the need for computer intervention at startup. Switching around a failed or switched-off unit is also autonomous. The JPL bus provides a map of all the active units for the host computer to read and use for fault management. With regard to timing, this enhanced bus recognizes coordinated timing on a spacecraft as critical and addresses this with a single source of absolute and relative time, which is broadcast to all units on the bus with synchronization maintained to the tens of nanoseconds. Each BIU consists of up to five programmable triggers, which may be programmed for synchronization of events within the spacecraft of instrument. All JPL-formatted data transmitted on the ring bus are automatically time-stamped.
The theme of this NASA Scientific and Technical Information Program Coordinating Council Meeting was standards and their formation and application. Topics covered included scientific and technical information architecture, the Open Systems Interconnection Transmission Control Protocol/Internet Protocol, Machine-Readable Cataloging (MARC) open system environment procurement, and the Government Information Locator Service.
Steady-state and frequency response calibration of a microfabricated heat-flux sensor have been completed. This sensor is batch fabricated using standard, micromachining techniques, allowing both miniaturization and the ability to create arrays of sensors and their corresponding interconnects. Both high-frequency and spatial response is desired, so the sensors are both thin and of small cross-sectional area. Thin-film, temperature-sensitive resistors are used as the active gauge elements. Two sensor configurations are investigated: (1) a Wheatstone-bridge using four resistors; and (2) a simple, two-resistor design. In each design, one resistor (or pair) is covered by a thin layer (5000 A) thermal barrier; the other resistor (or pair) is covered by a thick (5 microns) thermal barrier. The active area of a single resistor is 360 microns by 360 microns; the total gauge area is 1.5 mm square. The resistors are made of 2000 A-thick metal; and the entire gauge is fabricated on a 25 microns-thick flexible, polyimide substrate. Heat flux through the surface changes the temperature of the resistors and produces a corresponding change in resistance. Sensors were calibrated using two radiation heat sources: (1) a furnace for steady-state, and (2) a light and chopper for frequency response.
A document concisely describes a ring bus architecture for a proposed solid-state recorder (SSR) that would serve as buffer of data to be transmitted from a spacecraft to Earth. This architecture would afford fault tolerance needed for reliable operation in an anticipated high-radiation environment in which traditional SSRs cannot operate reliably. Features of the architecture include one or more controller boards and multiple memory boards interconnected in a ringlike topology. The interconnections would be high-speed serial links complying with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus). Accordingly, each controller and memory board would be equipped with an IEEE-1393-compliant ring-bus-interface unit. The ringlike topology and the multiplicity of memory boards (and, optionally, of controller boards) would afford the redundancy needed for fault tolerance. Each board would be a fault-containment region. The IEEE 1393 links could be routed so that the SSR would continue to function even in the event of multiple failures. This architecture would also support scalability over a wide range. In a fully redundant configuration, it could accommodate between 1 and 125 memory boards.
NASA needs solar arrays that are thin, flexible, and highly efficient; package compactly for launch; and deploy into large, structurally stable high-power generators. Inverted metamorphic multijunction (IMM) solar cells can enable these arrays, but integration of this thin crystalline cell technology presents certain challenges. The Thin Hybrid Interconnected Solar Array (THINS) technology allows robust and reliable integration of IMM cells into a flexible blanket comprising standardized modules engineered for easy production. The modules support the IMM cell by using multifunctional materials for structural stability, shielding, coefficient of thermal expansion (CTE) stress relief, and integrated thermal and electrical functions. The design approach includes total encapsulation, which benefits high voltage as well as electrostatic performance.
This paper outlines various mission requirements and technical approaches that support the potential use of portable computers in several defined activities within the Space Station Freedom (SSF) program. Specifically, the use of portable computers as consoles for both spacecraft control and payload applications is presented. Various issues and proposed solutions regarding the incorporation of portable computers within the program are presented. The primary issues presented regard architecture (standard interface for expansion, advanced processors and displays), integration (methods of high-speed data communication, peripheral interfaces, and interconnectivity within various support networks), and evolution (wireless communications and multimedia data interface methods).
New, innovative CubeSat mission concepts demand modern capabilities such as artificial intelligence and autonomy, constellation coordination, fault mitigation, and robotic servicing –all of which require vastly more processing resources than legacy systems are capable of providing. Enabling these domains within a scalable, configurable processing architecture is advantageous because it also allows for the flexibility to address varying mission roles, such as a command and data-handling system, a high-performance application processor extension, a guidance and navigation solution, or an instrument/sensor interface. This paper describes the NASA SpaceCube Intelligent Multi-Purpose System (IMPS), which allows mission developers to mix-and-match 1U (10 cm × 10 cm) CubeSat payloads configured for mission-specific needs. The central enabling component of the system architecture to address these concerns is the SpaceCube v3.0 Mini Processor. This single-board computer features the 20nm Xilinx Kintex UltraScale FPGA combined with a radiation-hardened FPGA monitor, and extensive IO to integrate and interconnect varying cards within the system. To unify the re-usable designs within this architecture, the CubeSat Card Standard was developed to guide design of 1U cards. This standard define spinout configurations, mechanical, and electrical specifications for 1U CubeSat cards, allowing the backplane and mechanical enclosure to be easily extended. NASA has developed several cards adhering to the standard (System-on-Chip, power card, etc.), which allows the flexibility to configure a payload from a common catalog of cards.
The National Aeronautics and Space Administration is developing a photon counting ground receiver for free-space optical communications. The receiver consists of a fiber interconnect, superconducting nanowire single photon counting detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. This receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency standard, which is used in the low photon flux communications regime, including on the upcoming Optical Artemis-2 Orion communications demonstration. The receiver architecture is modular, can be scaled for data rate, and is designed with primarily commercial-off-the-shelf technology. Two fiber interconnect and detector architectures are being prototyped. The first uses a few-mode-fiber coupled to a 16-channel SNSPD array and the second architecture uses a photonic lantern coupled to 7 single-pixel SNSPDs. Photon counting, symbol timing recovery, demodulation and decoding is done using several FPGA cards. This presentation describes the unique features of the ground receiver, performance test results, and challenges with using commercial SNSPDs in free-space optical communications.
CADAT place-and-route-in-two dimensions program (PR2D) is standard-cell automatic-layout program for generating large-scale-integrated/metal-oxidesemiconductor (LSI/MOS) arrays. PR2D translates logic designer's cell interconnection requirements into physically-defined MOS chip. PR2D reads input data, searches pin data file for data on each pattern type, generates placement of patterns, and interconnects patterns. As output, it generates artwork for layouts.
Qualification tests of solar cell modules are described. These modules continue to show improvement over earlier type modules tested. Cell cracking and delamination are less prevalent, and interconnect problems and electrical degradation from environmental testing are now rare.
Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.
SIFT (Software Implemented Fault Tolerance) is an ultrareliable computer for critical aircraft control applications that achieves fault tolerance by the replication of tasks among processing units. The main processing units are off-the-shelf minicomputers, with standard microcomputers serving as the interface to the I/O system. Fault isolation is achieved by using a specially designed redundant bus system to interconnect the processing units. Error detection and analysis and system reconfiguration are performed by software. Iterative tasks are redundantly executed, and the results of each iteration are voted upon before being used. Thus, any single failure in a processing unit or bus can be tolerated with triplication of tasks, and subsequent failures can be tolerated after reconfiguration. Independent execution by separate processors means that the processors need only be loosely synchronized, and a novel fault-tolerant synchronization method is described.
A flight test was conducted for preliminary evaluation of an aileron-rudder interconnect (ARI) control system for the F-14A airplane in the landing configuration. Two ARI configurations were tested in addition to the standard F-14 flight control system. Results of the flight test showed marked improvement in handling qualities when the ARI systems were used. Sideslip due to adverse yaw was considerably reduced, and airplane turn rate was more responsive to pilot lateral control inputs. Pilot comments substantiated the flight data and indicated that the ARI systems were superior to the standard control system in terms of pilot capability to make lateral offset corrections and heading changes on final approach.