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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Autonomous earth feature classification - Shuttle and aircraft flight test results

The Feature Identification and Location Experiment (FILE) flown on the Shuttle STS-2 mission November 12-14, 1981, tested a technique for autonomous real-time classification of selected earth features, i.e., water; bare land; vegetation; and clouds, snow, and ice. A second instrument, designed for aircraft flights, flew over regions of the west and east coasts of the United States and across the country. In each instrument, two bore-sighted CCD cameras image earth scenes in two spectral bands. Each camera includes a 100-element by 100-element detector array, and classification circuits. A simple algorithm and logic circuit provides classification decisions within a few microseconds. The experiment records the number of picture elements (pixels) representing each feature and the reflected solar radiation for each band. After flight, pixel-by-pixel classification images are constructed and compared with 70-mm color photographs taken simultaneously with the CCD-camera data.

Sivertson, W. E., Jr.↗
NASA NTRS2015

Radiation-Hardened Electronics for Advanced Communications Systems

Novel approach enables high-speed special-purpose processors Advanced reconfigurable and reprogrammable communication systems will require sub-130-nanometer electronics. Legacy single event upset (SEU) radiation-tolerant circuits are ineffective at speeds greater than 125 megahertz. In Phase I of this project, ICs, LLC, demonstrated new base-level logic circuits that provide SEU immunity for sub-130-nanometer high-speed circuits. In Phase II, the company developed an innovative self-restoring logic (SRL) circuit and a system approach that provides high-speed, SEU-tolerant solutions that are effective for sub-130-nanometer electronics scalable to at least 22-nanometer processes. The SRL system can be used in the design of NASA's next-generation special-purpose processors, especially reconfigurable communication processors.

Whitaker, Sterling↗
NASA NTRS1964

Self repair techniques

Computer simulation program for self-repairing system design - reliability improvement as compared to use of redundant logic circuits

SELF-REPAIRING SYSTEM↗
NASA NTRS1995

Combining Video Memory Operations

Designs of video random-access memory (VRAM) integrated circuits operating under control by external logic circuits simplified according to concept of combining two memory operations performed separately heretofore. Eliminates need for DRAM-refresh timers and counters, reducing amount of circuitry needed to control VRAM thereby reducing time needed to design VRAM. Simplification also reduces time needed to redesign DRAM-refresh logic circuitry when adapting VRAM design to another VRAM for which timing specifications different. Concept can be applied to VRAM clocking data out to display unit continuously.

Kania, Michael J.↗
NASA NTRS1970

Man-machine interactive system simplifies computer-aided circuit design

Langley interactive computerized circuit analysis capability /LICCA/ enables designer to draw electronic circuit diagrams on cathode ray tube screen. This information is submitted as input to user-selected circuit analysis program. LICCA accommodates binary logic circuits and circuits with discrete components, and monitors operator's instructions to detect errors.

Bavuso, S. J.↗
NASA NTRS1969

Self-starting circuit for switching regulators

Schematic is provided on a self-starting circuit for a switching regulator which uses a logic circuit to sense a change in output voltage and provides a correction signal for dc power sources. With this device, the total power consumed by the logic circuitry is held to a minimum, and the circuit receives the optimum regulated supply power.

Schraut, E. H.↗
NASA NTRS1966

One-count memory circuit prevents machine mode interaction

One-count memory logic circuit used with electromechanical counter-printer machines operates in either count or print mode. The circuit advances the counter when the machine is in the count mode and provides storage for the count pulse when the machine is in the print mode.

De~forest, B.↗
NASA NTRS1972

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Source record↗
NASA NTRS1988

Estimating Rates Of Single-Event Upsets

Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.

Zoutendyk, John A.↗
NASA NTRS1964

Computer circuit will fit on single silicon chip

A simplified computer logic circuit of two NAND/NOR gates and three additional inputs to accomplish the count and shift function is described. The circuit has capacity for parallel read-in, counting, serial shiftout, complement input and set and reset.

Smith, C.↗
NASA NTRS2009

"Glitch Logic" and Applications to Computing and Information Security

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

hardware vulnerabilities↗
NASA NTRS1985

Galileo internal electrostatic discharge program

The Galileo spacecraft which will orbit Jupiter in 1988 will encounter a very harsh environment of energetic electrons. These electrons will have sufficient energy to penetrate the spacecraft shielding, consequently depositing charges in the dielectric insulating materials or ungrounded conductors. The resulting electric field could exceed the breakdown strength of the insulating materials, producing discharges. The transients produced from these Internal Electrostatic Discharges (IESD) could, depending on their relative location, be coupled to nearby cables and circuits. These transients could change the state of logic circuits or degrade or even damage spacecraft components, consequently disrupting the operation of subsystems and systems of the Galileo spacecraft during its expected mission life. An extensive testing program was initiated for the purpose of understanding the potential threats associated with these IESD events. Data obtained from these tests were used to define design guidelines.

Leung, P. L.↗
NASA NTRS1990

Pass transistor implementations of multivalued logic

A simple straight-forward Karnaugh map logic design procedure for realization of multiple-valued logic circuits is presented in this paper. Pass transistor logic gates are used to realize multiple-valued networks. This work is an extension of pass transistor implementations for binary-valued logic.

Maki, G.↗
NASA NTRS1965

Simple circuit performs binary addition and subtraction

Ripple adder reduces the number of logic circuits required to preform binary addition and subtraction. The adder uses dual input and delayed output flip-flops in one register. The contents of this register are summed with those of a standard register through conventional AND/gates.

Cliff, R. A.↗