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User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.
Topics covered include: Miniature Intelligent Sensor Module; "Smart" Sensor Module; Portable Apparatus for Electrochemical Sensing of Ethylene; Increasing Linear Dynamic Range of a CMOS Image Sensor; Flight Qualified Micro Sun Sensor; Norbornene-Based Polymer Electrolytes for Lithium Cells; Making Single-Source Precursors of Ternary Semiconductors; Water-Free Proton-Conducting Membranes for Fuel Cells; Mo/Ti Diffusion Bonding for Making Thermoelectric Devices; Photodetectors on Coronagraph Mask for Pointing Control; High-Energy-Density, Low-Temperature Li/CFx Primary Cells; G4-FETs as Universal and Programmable Logic Gates; Fabrication of Buried Nanochannels From Nanowire Patterns; Diamond Smoothing Tools; Infrared Imaging System for Studying Brain Function; Rarefying Spectra of Whispering-Gallery-Mode Resonators; Large-Area Permanent-Magnet ECR Plasma Source; Slot-Antenna/Permanent-Magnet Device for Generating Plasma; Fiber-Optic Strain Gauge With High Resolution And Update Rate; Broadband Achromatic Telecentric Lens; Temperature-Corrected Model of Turbulence in Hot Jet Flows; Enhanced Elliptic Grid Generation; Automated Knowledge Discovery From Simulators; Electro-Optical Modulator Bias Control Using Bipolar Pulses; Generative Representations for Automated Design of Robots; Mars-Approach Navigation Using In Situ Orbiters; Efficient Optimization of Low-Thrust Spacecraft Trajectories; Cylindrical Asymmetrical Capacitors for Use in Outer Space; Protecting Against Faults in JPL Spacecraft; Algorithm Optimally Allocates Actuation of a Spacecraft; and Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets.
The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.
Abstract The synthesis of soft matter intelligence with circuit‐driven logic has enabled a new class of robots that perform complex tasks or conform to specialized form factors in unique ways that cannot be realized through conventional designs. Translating this hybrid approach to fluidic systems, the present work addresses the need for sheet‐based circuit materials by leveraging the innate porosity of foam—a soft material—to develop pneumatic components that support digital logic, mixed‐signal control, and analog force sensing in wearables and soft robots. Analytical tools and experimental techniques developed in this work serve to elucidate compressible gas flow through porous sheets, and to inform the design of centimeter‐sized foam resistors with fluidic resistances on the order of 10 9 Pa s m −3 . When embedded inside soft robots and wearables, these resistors facilitate diverse functionalities spanning both sensing and control domains, including digital logic using textile logic gates, digital‐to‐analog signal conversion using ladder networks, and analog sensing of forces up to 40 N via compression‐induced changes in resistance. By combining features of both circuit‐based and materials‐based approaches, foam‐enabled fluidic circuits serve as a useful paradigm for future hybrid robotic architectures that fully embody the sensing and computing capabilities of soft fluidic materials.
Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.
One dimensional cellular logic arrays fault circumvention by bypass switching out defective cells in cascade
Abstract Simulations of the land surface carbon cycle typically compress functional diversity into a small set of plant functional types (PFT), with parameters defined by the average value of measurements of functional traits. In most earth system models, all wild plant life is represented by between five and 14 PFTs and a typical grid cell (≈100 × 100 km) may contain a single PFT. Model logic applied to this coarse representation of ecological functional diversity provides a reasonable proxy for the carbon cycle, but does not capture the non‐linear influence of functional traits on productivity. Here we show through simulations using the Energy Exascale Land Surface Model in 15 diverse terrestrial landscapes, that better accounting for functional diversity markedly alters predicted total carbon uptake. The shift in carbon uptake is as great as 30% and 10% in boreal and tropical regions, respectively, when compared to a single PFT parameterized with the trait means. The traits that best predict gross primary production vary based on vegetation phenology, which broadly determines where traits fall within the global distribution. Carbon uptake is more closely associated with specific leaf area for evergreen PFTs and the leaf carbon to nitrogen ratio in deciduous PFTs.
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET
Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.
Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.
To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.
The National Spherical Torus Experiment Upgrade (NSTX-U) centerstack casing surrounds the central magnet core of NSTXU. It provides the inner vacuum boundary of the plasma chamber and supports the radially inboard plasma facing components lining the plasma chamber. The casing is supported like a cantilever, fixed at the lower flange by a connection to the TF Bundle through a G-10 ring. It is flexibly supported at the top by bellows, and insulated shims intended to react the largest part of the inventory of the disruption loads at the upper support, thereby protecting the upper and lower connections from excessive loads. A large part of the qualification of the casing and tiles requires addressing and quantifying disruption loads. These have been estimated based on extensions of the behavior of NSTX during its run period roughly 15 years ago. Structural qualification of the Upgrade used these estimates of the loading as input to calculations to demonstrate adequacy for a “most probable” disruption. The estimates are included in a requirements document to guide conservative design of all components loaded by disruptions. However, the changes made for the upgrade made the extrapolation of disruption behavior uncertain. Disruptions include axisymmetric loading from axisymmetric currents induced in the vessel shells. In addition, more complex currents called Halo currents are a result of plasma poloidal currents impinging on the casing. The halo currents add another layer of uncertain behavior and net lateral loading to the casing. As a result, NSTX-U is equipped with a number of instruments intended to assess the nature and severity of disruptions. The casing shims are required for lateral support of the casing, but these have also been converted to load cells to provide another measure of the magnitude of symmetric and asymmetric loading. Some of the logic in the development of the requirements document are presented. Electromagnetic analysis of axisymmetric and halo loading is described. Global simulations of the casing transient dynamic response, and local analysis and testing of the shim/load cell are included. The shim load cells and other instrumentation will be an important guide in planning NSTX-U experiments beyond its next run period expected in late 2026 or early 2027.
Several beta-adrenergic receptor (bAR) agonists are known to cause hypertrophy of skeletal muscle tissue. Because it seems logical that these agonists exert their action on muscle through stimulation of cAMP synthesis, five bAR agonists encompassing a range in activity from strong to weak were evaluated for their ability to stimulate cAMP accumulation in embryonic chicken skeletal muscle cells in culture. Two strong agonists (epinephrine and isoproterenol), one moderate agonist (albuterol), and two weak agonists known to cause hypertrophy in animals (clenbuterol and cimaterol) were studied. Dose response curves were determined over six orders of magnitude in concentration for each agonist, and values were determined for their maximum stimulation of cAMP synthesis rate (Bmax) and the agonist concentration at which 50% stimulation of cAMP synthesis (EC50) occurred. Bmax values decreased in the following order: isoproterenol, epinephrine, albuterol, cimaterol, clenbuterol. Cimaterol and clenbuterol at their Bmax levels were approximately 15-fold weaker than isoproterenol in stimulating the rate of cAMP synthesis. In addition, the EC50 values for isoproterenol, cimaterol, clenbuterol, epinephrine, and albuterol were 360 nM, 630 nM, 900 nM, 2,470 nM, and 3,650 nM, respectively. Finally, dose response curves show that the concentrations of cimaterol and clenbuterol in culture media at concentrations known to cause significant muscle hypertrophy in animals had no detectable effect on stimulation of CAMP accumulation in chicken skeletal muscle cells.
Due to the common use of Flash technology in many commercial and industrial Programmable Logic Devices (PLDs) such as FPGAs and mixed-signal microcontrollers, flash technology is being utilized in fuzed munition applications. This presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. Initial test results based on a study of charge loss in flash cells in an FPGA device is presented. Statistical data taken from a small sample set indicates quantifiable charge loss for devices stored at both room temperature and 150 C. Initial evaluation of the distribution of threshold voltage in a large sample set (800 devices) is presented. The magnitude of charge loss from exposure to electrostatic discharge and electromagnetic fields is measured and presented. Simulated data (and measured data as available) resultant from harsh-environment testing (neutron, heavy ion, EMP) is presented.
Due to the common use of Flash technology in many commercial and industrial Programmable Logic Devices (PLDs) such as FPGAs and mixed-signal microcontrollers, flash technology is being utilized in fuzed munition applications. This presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. Initial test results based on a study of charge loss in flash cells in an FPGA device is presented. Statistical data taken from a small sample set indicates quantifiable charge loss for devices stored at both room temperature and 150 C. Initial evaluation of the distribution of threshold voltage in a large sample set (800 devices) is presented. The magnitude of charge loss from exposure to electrostatic discharge and electromagnetic fields is measured and presented. Simulated data (and measured data as available) resultant from harsh-environment testing (neutron, heavy ion, EMP) is presented.
We report that the hybrid kinetic-ion fluid-electron plasma model is widely used to study challenging multi-scale problems in space and laboratory plasma physics. Here, a novel conservative scheme for this model employing implicit particle-in-cell techniques is extended to arbitrary coordinate systems via curvilinear maps from logical to physical space. The scheme features a fully non-linear electromagnetic formulation with a multi-rate time advance - including sub-cycling and orbit-averaging for the kinetic ions. By careful choice of compatible particle-based kinetic-ion and mesh-based fluid-electron discretizations in curvilinear coordinates, as well as particle-mesh interpolations and implicit midpoint time advance, the scheme is proven to conserve total energy for arbitrary curvilinear meshes. In the electrostatic limit, the method is also proven to conserve total momentum for arbitrary curvilinear meshes. Although momentum is not conserved for arbitrary curvilinear meshes in the electromagnetic case, it is for an important subset of Cartesian tensor-packed meshes. The scheme and its novel conservation properties are demonstrated for several challenging numerical problems using different curvilinear meshes, including a merging flux-rope simulation for a space weather application, and a helical m = 1 mode simulation for magnetic fusion energy application.
Fluidic logic elements to control firing and extinction of plasma matrix display system cells with constant electrical power supply
A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.