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At least 91 records · Page 5

Recoverable distributed shared virtual memory

The problem of rollback recovery in distributed shared virtual environments, in which the shared memory is implemented in software in a loosely coupled distributed multicomputer system, is examined. A user-transparent checkpointing recovery scheme and a new twin-page disk storage management technique are presented for implementing recoverable distributed shared virtual memory. The checkpointing scheme can be integrated with the memory coherence protocol for managing the shared virtual memory. The twin-page disk design allows checkpointing to proceed in an incremental fashion without an explicit undo at the time of recovery. The recoverable distributed shared virtual memory allows the system to restart computation from a checkpoint without a global restart.

Wu, Kun-Lung

Flexible format generator design techniques.

Flexible format generator for manned spacecraft data management system designed with memory for data sampling formats, emphasizing software counters and power strobing

Rathbone, W. M.

Multipurpose panel, phase 1, study report

The feasibility of a multipurpose panel which provides a programmable electronic display for changeable panel nomenclature, multiplexes similar indicator display signals to the signal display, and demultiplexes command signals is examined. Topics discussed include: electronic display technology, miniaturized electronic and memory devices, and data management systems which employ digital address and multiplexing.

Parkin, W.

The solution of the three-dimensional viscous-compressible Navier-Stokes equations on a vector computer

The development of a vectorized computer code for the solution of the three-dimensional viscous-compressible Navier-Stokes equations is described. The code is applied on the CDC STAR-100 vector computer which is capable of achieving high result rates when a high degree of parallelism is present in the computations. The computational technique is an explicit time-split MacCormack predictor-corrector algorithm. Since a large volume of data is processed and virtual memory utilized, a data management scheme based on interleaving is used. The program has been applied to obtain the solution of the laminar supersonic flow about a family of three-dimensional corners. The equations of motion are expressed in a generalized form relative to a uniform rectangular computational domain. The metric coefficient and boundary conditions must be supplied for the corresponding physical domain. For calculations with 30,000 grid points, a computational rate of 0.00015 seconds per grid point per time step is observed.

Smith, R. E.

Lunar Passive Fuel Cell Technologies: Evaporator + Fluid Polishing Elements

This project investigates key elements of a fully-passive, fuel-cell based, surface power generation concept. The overall concept replaces the actively pumped thermal management of a state of the art (SOA) fuel cell/electrolyzer stack with a passive 2-phase thermosyphon for heat transport and a passive shape memory actuating radiator for temperature management. The elements of the concept investigated in this project are: Evaporator Element: Evaluating the compatibility of common fuel-cell interconnect materials in the evaporator of a 2-phase water thermosyphon Fluid Polishing element: The use of membrane gas separation and resin water polishing to address non-condensable gas removal and water purity.

Fuel Cell

Passive fuel-Cell Surface power System (PaCeSS)

This effort produces a fully-passive surface power generation capability for fuel cell technology. The concept replaces the actively pumped thermal management of a state of the art (SOA) fuel cell/electrolyzer stack with a passive 2-phase thermosyphon for heat transport and a passive shape memory actuating radiator for temperature management.

Fuel Cell

Dynamic object management for distributed data structures

In distributed-memory multiprocessors, remote memory accesses incur larger delays than local accesses. Hence, insightful allocation and access of distributed data can yield substantial performance gains. The authors argue for the use of dynamic data management policies encapsulated within individual distributed data structures. Distributed data structures offer performance, flexibility, abstraction, and system independence. This approach is supported by data from a trace-driven simulation study of parallel scientific benchmarks. Experimental data on memory locality, message count, message volume, and communication delay suggest that data-structure-specific data management is superior to a single, system-imposed policy.

Totty, Brian K.

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K

Planning Mars Memory: Learning from the Mer Mission

Knowledge management for space exploration is part of a multi-generational effort at recognizing, preserving and transmitting learning. Each mission should be built on the learning, of both successes and failures, derived from previous missions. Knowledge management begins with learning, and the recognition that this learning has produced knowledge. The Mars Exploration Rover mission provides us with an opportunity to track how learning occurs, how it is recorded, and whether the representations of this learning will be optimally useful for subsequent missions. This paper focuses on the MER science and engineering teams during Rover operations. A NASA team conducted an observational study of the ongoing work and learning of the these teams. Learning occurred in a wide variety of areas: how to run two teams on Mars time for three months; how to use the instruments within the constraints of the martian environment, the deep space network and the mission requirements; how to plan science strategy; how best to use the available software tools. This learning is preserved in many ways. Primarily it resides in peoples memories, to be carried on to the next mission. It is also encoded in stones, in programming sequences, in published reports, and in lessons learned activities, Studying learning and knowledge development as it happens allows us to suggest proactive ways of capturing and using it across multiple missions and generations.

Linde, Charlotte

Multi-processing system study

The results are summarized of a multiprocessor systems design review. The systems were reviewed against use in a space station environment. The proposed designs were evaluated from a systems viewpoint in general and from the systems software in particular. The recommendations resulting from this evaluation are anticipated to be considered for the design of a multiprocessing system built around a SUMC. Two multiprocessing system designs were reviewed. The designs reviewed were highly functional and many questions could not be answered. However, several major issues were uncovered which could be evaluated to some detail, and which could greatly impact the SUMC-MP design. The major issues relevant to a multiprocessing system design revolve around the following functions: (1) Storage Management, (2) Processor Management, (3) Intermodule Communication, (4) Memory Access Interference, (5) System Efficiency, and (6) System Recovery/Reliability.

Source record

Future MAUS payload and the TWIN-MAUS configuration

The German MAUS project (materials science autonomous experiments in weightlessness) was initiated in 1979 for optimum utilization of NASA's Get Away Special (GAS) program. The standard MAUS system was developed to meet GAS requirements and can accommodate a wide variety of GAS-type experiments. The system offers a range of services to experimenters within the framework of standardized interfaces. Four MAUS payloads being prepared for future space shuttle flight opportunities are described. The experiments include critical Marangoni convection, oscillatory Marangoni convection, pool boiling, and gas bubbles in glass melts. Scientific objectives as well as equipment hardware are presented together with recent improvements to the MAUS standard system, e.g., a new experiment control and data management unit and a semiconductor memory. A promising means of increasing resources in the field of GAS experiments is the interconnection of GAS containers. This important feature has been studied to meet the challenge of future advanced payloads. In the TWIN-MAUS configuration, electrical power and data will be transferred between two containers mounted adjacent to each other.

Staniek, S.

The Build System - Integration and management of large software avionic systems

The Build System comprises the software tools and procedures creating the flight memory load for the Space Shuttle Backup Flight System. The system has six functions: (1) configuration management, which insures that the memory load contains the proper modules, all clearly marked; (2) source translation, which translates the source code into a relocatable machine code; (3) module integration, which combines and assigns memory locations to all the object modules produced in source translation; (4) static code analysis, which verifies the integration process; (5) deliverables generation, which yields release documentation and deliverable items; and (6) release maintenance, which controls all system patches subsequent to release. Further developments will include more automation in the producing of patches from source-code updates and system requirements for tracking.

Mayer, J. T. B.

Radiation-Hardened Solid-State Drive

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Sheldon, Douglas J.

Multiplexer/Demultiplexer Loading Tool (MDMLT)

The purpose of the MDMLT is to improve the reliability and speed of loading multiplexers/demultiplexers (MDMs) in the Software Development and Integration Laboratory (SDIL) by automating the configuration management (CM) of the loads in the MDMs, automating the loading procedure, and providing the capability to load multiple or all MDMs concurrently. This loading may be accomplished in parallel, or single MDMs (remote). The MDMLT is a Web-based tool that is capable of loading the entire International Space Station (ISS) MDM configuration in parallel. It is able to load Flight Equivalent Units (FEUs), enhanced, standard, and prototype MDMs as well as both EEPROM (Electrically Erasable Programmable Read-Only Memory) and SSMMU (Solid State Mass Memory Unit) (MASS Memory). This software has extensive configuration management to track loading history, and the performance improvement means of loading the entire ISS MDM configuration of 49 MDMs in approximately 30 minutes, as opposed to 36 hours, which is what it took previously utilizing the flight method of S-Band uplink. The laptop version recently added to the MDMLT suite allows remote lab loading with the CM of information entered into a common database when it is reconnected to the network. This allows the program to reconfigure the test rigs quickly between shifts, allowing the lab to support a variety of onboard configurations during a single day, based on upcoming or current missions. The MDMLT Computer Software Configuration Item (CSCI) supports a Web-based command and control interface to the user. An interface to the SDIL File Transfer Protocol (FTP) server is supported to import Integrated Flight Loads (IFLs) and Internal Product Release Notes (IPRNs) into the database. An interface to the Monitor and Control System (MCS) is supported to control the power state, and to enable or disable the debug port of the MDMs to be loaded. Two direct interfaces to the MDM are supported: a serial interface (debug port) to receive MDM memory dump data and the calculated checksum, and the Small Computer System Interface (SCSI) to transfer load files to MDMs with hard disks. File transfer from the MDM Loading Tool to EEPROM within the MDM is performed via the MILSTD- 1553 bus, making use of the Real- Time Input/Output Processors (RTIOP) when using the rig-based MDMLT, and via a bus box when using the laptop MDMLT. The bus box is a cost-effective alternative to PC-1553 cards for the laptop. It is noted that this system can be modified and adapted to any avionic laboratory for spacecraft computer loading, ship avionics, or aircraft avionics where multiple configurations and strong configuration management of software/firmware loads are required.

Brewer, Lenox Allen

Computer Sciences and Data Systems, volume 1

Topics addressed include: software engineering; university grants; institutes; concurrent processing; sparse distributed memory; distributed operating systems; intelligent data management processes; expert system for image analysis; fault tolerant software; and architecture research.

Source record

HTMT-class Latency Tolerant Parallel Architecture for Petaflops Scale Computation

Computational Aero Sciences and other numeric intensive computation disciplines demand computing throughputs substantially greater than the Teraflops scale systems only now becoming available. The related fields of fluids, structures, thermal, combustion, and dynamic controls are among the interdisciplinary areas that in combination with sufficient resolution and advanced adaptive techniques may force performance requirements towards Petaflops. This will be especially true for compute intensive models such as Navier-Stokes are or when such system models are only part of a larger design optimization computation involving many design points. Yet recent experience with conventional MPP configurations comprising commodity processing and memory components has shown that larger scale frequently results in higher programming difficulty and lower system efficiency. While important advances in system software and algorithms techniques have had some impact on efficiency and programmability for certain classes of problems, in general it is unlikely that software alone will resolve the challenges to higher scalability. As in the past, future generations of high-end computers may require a combination of hardware architecture and system software advances to enable efficient operation at a Petaflops level. The NASA led HTMT project has engaged the talents of a broad interdisciplinary team to develop a new strategy in high-end system architecture to deliver petaflops scale computing in the 2004/5 timeframe. The Hybrid-Technology, MultiThreaded parallel computer architecture incorporates several advanced technologies in combination with an innovative dynamic adaptive scheduling mechanism to provide unprecedented performance and efficiency within practical constraints of cost, complexity, and power consumption. The emerging superconductor Rapid Single Flux Quantum electronics can operate at 100 GHz (the record is 770 GHz) and one percent of the power required by convention semiconductor logic. Wave Division Multiplexing optical communications can approach a peak per fiber bandwidth of 1 Tbps and the new Data Vortex network topology employing this technology can connect tens of thousands of ports providing a bi-section bandwidth on the order of a Petabyte per second with latencies well below 100 nanoseconds, even under heavy loads. Processor-in-Memory (PIM) technology combines logic and memory on the same chip exposing the internal bandwidth of the memory row buffers at low latency. And holographic storage photorefractive storage technologies provide high-density memory with access a thousand times faster than conventional disk technologies. Together these technologies enable a new class of shared memory system architecture with a peak performance in the range of a Petaflops but size and power requirements comparable to today's largest Teraflops scale systems. To achieve high-sustained performance, HTMT combines an advanced multithreading processor architecture with a memory-driven coarse-grained latency management strategy called "percolation", yielding high efficiency while reducing the much of the parallel programming burden. This paper will present the basic system architecture characteristics made possible through this series of advanced technologies and then give a detailed description of the new percolation approach to runtime latency management.

Sterling, Thomas

Rocket Engine Health Management: Early Definition of Critical Flight Measurements

The NASA led Space Launch Initiative (SLI) program has established key requirements related to safety, reliability, launch availability and operations cost to be met by the next generation of reusable launch vehicles. Key to meeting these requirements will be an integrated vehicle health management ( M) system that includes sensors, harnesses, software, memory, and processors. Such a system must be integrated across all the vehicle subsystems and meet component, subsystem, and system requirements relative to fault detection, fault isolation, and false alarm rate. The purpose of this activity is to evolve techniques for defining critical flight engine system measurements-early within the definition of an engine health management system (EHMS). Two approaches, performance-based and failure mode-based, are integrated to provide a proposed set of measurements to be collected. This integrated approach is applied to MSFC s MC-1 engine. Early identification of measurements supports early identification of candidate sensor systems whose design and impacts to the engine components must be considered in engine design.

Christenson, Rick L.