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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Benchmarking Quantum Processor Performance through Quantum Distance Metrics Over An Algorithm Suite

Quantum computing is poised to solve computational paradigms that classical computing could never feasibly reach. Tasks such as prime factorization to Quantum Chemistry are examples of classically difficult problems that have analogous algorithms that are sped up on quantum computers. To attain this computational advantage, we must first traverse the noisy intermediate scale quantum (NISQ) era, in which quantum processors suffer from compounding noise factors that can lead to unreliable algorithm induction producing noisy results. We describe QASMBench, a suite of QASM-level (Quantum assembly language) benchmarks that challenge all realisable angles of quantum processor noise. We evaluate a large portion of these algorithms by performing density matrix tomography on 14 IBMQ Quantum devices.

Stein, Samuel A.↗
DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗
DOE OSTI2024

Probing Quantum Telecloning on Superconducting Quantum Processors

Quantum information cannot be perfectly cloned, but approximate copies of quantum information can be generated. Quantum telecloning combines approximate quantum cloning, more typically referred to as quantum cloning, and quantum teleportation. Quantum telecloning allows approximate copies of quantum information to be constructed by separate parties, using the classical results of a Bell measurement made on a prepared quantum telecloning state. Quantum telecloning can be implemented as a circuit on quantum computers using a classical coprocessor to compute classical feedforward instructions using if statements based on the results of a midcircuit Bell measurement in real time. We present universal symmetric optimal 1 → M telecloning circuits and experimentally demonstrate these quantum telecloning circuits for M = 2 up to M = 10, natively executed with real-time classical control systems on IBM Quantum superconducting processors, known as dynamic circuits. We perform the cloning procedure on many different message states across the Bloch sphere, on seven IBM Quantum processors, optionally using the error suppression technique X–X sequence digital dynamical decoupling. Two circuit optimizations are utilized: one that removes ancilla qubits for M = 2,3 , and one that reduces the total number of gates in the circuit but still uses ancilla qubits. Parallel single-qubit tomography with maximum likelihood estimation density matrix reconstruction is used in order to compute the mixed-state density matrices of the clone qubits, and clone quality is measured using quantum fidelity. These results present one of the largest and most comprehensive noisy intermediate-scale quantum computer experimental analyses on (single qubit) quantum telecloning to date. The clone fidelity sharply decreases to 0.5 for M > 5 , but for M = 2 , we are able to achieve a mean clone fidelity of up to 0.79 using dynamical decoupling.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Realization and Calibration of Continuously Parameterized Two-Qubit Gates on a Trapped-Ion Quantum Processor

Continuously parameterized two-qubit gates are a key feature of state-of-the-art trapped-ion quantum processors, as they have favorable error scalings and show distinct improvements in circuit performance over more restricted maximally entangling gatesets. In this work, we provide a comprehensive and pedagogical discussion on how to practically implement these continuously parameterized Mølmer–Sørensen gates on the Quantum Scientific Computing Open User Testbed, a low-level trapped-ion processor. To generate the arbitrary entangling angles, θ, we simply scale the amplitude of light used to generate the entanglement. However, doing so requires careful consideration of amplifier saturation as well as the variable light shifts that result. As such, we describe a method to calibrate and cancel the dominant fourth-order effects, followed by a dynamic virtual phase advance during the gate to cancel any residual light shifts, and find a linear scaling between θ and the residual light shift. Once we have considered and calibrated these effects, we demonstrate performance improvement with decreasing θ. Finally, we describe nuances of hardware control to transform the XX-type interaction of the arbitrary-angle Mølmer–Sørensen gate into a phase-agnostic and crosstalk-mitigating ZZ interaction.

Yale, Christopher Gordon [Sandia National Laborato↗
DOE OSTI2023

Modelling integrated quantum frequency processors towards robust quantum networks

Frequency-encoded quantum information offers intriguing opportunities for quantum communications networks, with the quantum frequency processor (QFP) paradigm promising scalable construction of quantum gates. Yet all experimental demonstrations to date have relied on discrete fiber-optic components that occupy significant physical space and impart appreciable loss. We introduce a model for designing QFPs comprising microring resonator-based pulse shapers and integrated phase modulators. We estimate the performance of frequency-bin Hadamard gates, finding high fidelity values sustained for relatively wide-bandwidth frequency bins. Our simple model and can be extended to other material platforms, providing a design tool for future frequency processors in integrated photonics.

Nussbaum, Benjamin↗
DOE OSTI2018

Graphic Processor Realization of the Formal Solution of the Problem of Radiation Transfer in the Neutron Star Atmosphere

The realization (on the CUDA platform) of the search for the formal solution to the problem of radiation transfer in the strongly magnetized plasma in the atmosphere of a neutron star on graphic processors with the CUDA architecture. The solution is obtained using the Galerkin method with finite elements. The realization of graphic processors makes it possible to substantially accelerate computations in constructing models for the atmospheres of neutron stars.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2015

Towards an Application-Specific Thermal Energy Model of Current Processors

Recent developments of high-end processors recognize temperature monitoring and tuning as one of the main challenges towards achieving higher performance given the growing power and temperature constraints. To address this challenge, one needs both suitable thermal energy abstraction and corresponding instrumentation. Our model is based on application-specific parameters such as power consumption, execution time, and asymptotic temperature as well as hardware-specific parameters such as half time for thermal rise or fall. As observed with our out-of-band instrumentation and monitoring infrastructure, the temperature changes follow a relatively slow capacitor-style charge-discharge process. Therefore, we use the lumped thermal model that initiates an exponential process whenever there is a change in processor’s power consumption. Initial experiments with two codes – Firestarter and Nekbone – validate our application-specific thermal model and demonstrate its use for analyzing and potentially improving the balance between temperature, power, and performance.

Getov, Vladimir S.↗
DOE OSTI2019

SMuRF Processor

This repository contains the SMuRF data processor. This processor receive each data frame from coming from the SMuRF FPGA, and average the data by a configurable number of samples.

Vasquez, Jesus↗
DOE OSTI2018

Image Matrix Processor for Volumetric Computations Final Report CRADA No. TSB-1148-95

The development of an Image Matrix Processor (IMP) was proposed that would provide an economical means to perform rapid ray-tracing processes on volume "Giga Voxel" data sets. This was a multi-phased project. The objective of the first phase of the IMP project was to evaluate the practicality of implementing a workstation-based Image Matrix Processor for use in volumetric reconstruction and rendering using hardware simulation techniques. Additionally, ARACOR and LLNL worked together to identify and pursue further funding sources to complete a second phase of this project.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Efficient Scalable Tomography of Many-Qubit Quantum Processors

Quantum computing has the potential to realize powerful and revolutionary applications. A quantum computer can, in theory, solve certain problems exponentially faster than its classical counterparts. The current state of the art devices, however, are too small and noisy to practically realize this goal. An important tool for the advancement of quantum hardware, called model-based characterization, seeks to learn what types of noise are exhibited in a quantum processor. This technique, however, is notoriously difficult to scale up to even modest numbers of qubit, and has been limited to just 2 qubits until now. In this report, we present a novel method for performing model-based characterization, or tomography, on a many-qubit quantum processor. We consider up to 10 qubits, but the technique is expected to scale to even larger systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Efficient, Predictive Tomography of Multi-Qubit Quantum Processors

After decades of R&D, quantum computers comprising more than 2 qubits are appearing. If this progress is to continue, the research community requires a capability for precise characterization (“tomography”) of these enlarged devices, which will enable benchmarking, improvement, and finally certification as mission-ready. As world leaders in characterization -- our gate set tomography (GST) method is the current state of the art – the project team is keenly aware that every existing protocol is either (1) catastrophically inefficient for more than 2 qubits, or (2) not rich enough to predict device behavior. GST scales poorly, while the popular randomized benchmarking technique only measures a single aggregated error probability. This project explored a new insight: that the combinatorial explosion plaguing standard GST could be avoided by using an ansatz of few-qubit interactions to build a complete, efficient model for multi-qubit errors. We developed this approach, prototyped it, and tested it on a cutting-edge quantum processor developed by Rigetti Quantum Computing (RQC), a US-based startup. We implemented our new models within Sandia’s PyGSTi open-source code, and tested them experimentally on the RQC device by probing crosstalk. We found two major results: first, our schema worked and is viable for further development; second, while the Rigetti device is indeed a “real” 8-qubit quantum processor, its behavior fluctuated significantly over time while we were experimenting with it and this drift made it difficult to fit our models of crosstalk to the data.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Mixed core processor unit

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗
DOE OSTI2022

High speed two-dimensional event detection and imaging using an analog interface and a massively parallel processor

A quantitative pulse count (event detection) algorithm with linearity to high count rates is accomplished by combining a high-speed, high frame rate camera with simple logic code run on a massively parallel processor such as a GPU or a FPGA. The parallel processor elements examine frames from the camera pixel by pixel to find and tag events or count pulses. The tagged events are combined to form a combined quantitative event image.

Waugh, Justin↗
DOE OSTI2016

A 65 nm CMOS analog processor with zero dead time for future pixel detectors

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm –2 s –1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. In conclusion, a thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Small-world complex network generation on a digital quantum processor

Abstract Quantum cellular automata (QCA) evolve qubits in a quantum circuit depending only on the states of their neighborhoods and model how rich physical complexity can emerge from a simple set of underlying dynamical rules. The inability of classical computers to simulate large quantum systems hinders the elucidation of quantum cellular automata, but quantum computers offer an ideal simulation platform. Here, we experimentally realize QCA on a digital quantum processor, simulating a one-dimensional Goldilocks rule on chains of up to 23 superconducting qubits. We calculate calibrated and error-mitigated population dynamics and complex network measures, which indicate the formation of small-world mutual information networks. These networks decohere at fixed circuit depth independent of system size, the largest of which corresponding to 1,056 two-qubit gates. Such computations may enable the employment of QCA in applications like the simulation of strongly-correlated matter or beyond-classical computational demonstrations.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Characterization of Quantum Frequency Processors

Frequency-bin qubits possess unique synergies with wavelength-multiplexed lightwave communications, suggesting valuable opportunities for quantum networking with the existing fiber-optic infrastructure. Although the coherent manipulation of frequency-bin states requires highly controllable multi-spectral-mode interference, the quantum frequency processor (QFP) provides a scalable path for gate synthesis leveraging standard telecom components. Here, we summarize the state of the art in experimental QFP characterization. Distinguishing between physically motivated “open box” approaches that treat the QFP as a multiport interferometer, and “black box” approaches that view the QFP as a general quantum operation, we highlight the assumptions and results of multiple techniques, including quantum process tomography of a tunable beamsplitter—to our knowledge the first full process tomography of any frequency-bin operation. Our findings should inform future characterization efforts as the QFP increasingly moves beyond proof-of-principle tabletop demonstrations toward integrated devices and deployed quantum networking experiments.

42 ENGINEERING↗