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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5

Least reliable bits coding (LRBC) for high data rate satellite communications

LRBC, a bandwidth efficient multilevel/multistage block-coded modulation technique, is analyzed. LRBC uses simple multilevel component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Soft-decision multistage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Analytical expressions and tight performance bounds are used to show that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of BPSK. The relative simplicity of Galois field algebra vs the Viterbi algorithm and the availability of high-speed commercial VLSI for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.

Vanderaar, Mark↗

A Library of Rad Hard Mixed-Voltage/Mixed-Signal Building Blocks for Integration of Avionics Systems for Deep Space

To build the sensor intensive system-on-a-chip for the next generation spacecrafts for deep space, Center for Integration of Space Microsystems at JPL (CISM) takes advantage of the lower power rating and inherent radiation resistance of Silicon on Insulator technology (SOI). We are developing a suite of mixed-voltage and mixed-signal building blocks in Honeywell's SOI process that can enable the rapid integration of the next generation avionics systems with lower power rating, higher reliability, longer life, and enhanced radiation tolerance for spacecrafts such as the Europa Orbiter and Europa Lander. The mixed-voltage building blocks are predominantly for design of adaptive power management systems. Their design centers around an LDMOS structure that is being developed by Honeywell, Boeing Corp, and the University of Idaho. The mixed-signal building blocks are designed to meet the low power, extreme radiation requirement of deep space applications. These building blocks are predominantly used to interface analog sensors to the digital CPU of the next generation avionics system on a chip. Additional information is contained in the original extended abstract.

Mojarradi, M. M.↗

Ultra-long-life spacecraft for long duration space exploration missions

The predominant failure mode in an ultra longlife system is the wear-out of components. In order to survive long duration missions, current fault tolerant design techniques would require excessive number of redundant components. This paper describes a more efficient fault tolerant avionics system architecture that requires much less redundant components. This architecture employs generic function blocks that can be programmed to replace a wide variety of components in-flight. Hence, each individual generic block is essentially equivalent to almost an entire redundant string of components in the conventional approach. In that way, the ultra long-life system can achieve much higher level of reliability while carrying much less components. On the other hand, due to the programmability of the generic redundant blocks, the physical location of a specific component might not be pre-determined. Therefore, wireless interconnection is employed to provide the necessary flexibility in connectivity. A testbed of this architecture is being developed at the Jet Propulsion Laboratory.

return missions↗

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Source record↗

Analysis of transmission error effects on the transfer of real-time simulation data

An analysis was made to determine the effect of transmission errors on the quality of data transferred from the Terminal Area Air Traffic Model to a remote site. Data formating schemes feasible within the operational constraints of the data link were proposed and their susceptibility to both random bit error and to noise burst were investigated. It was shown that satisfactory reliability is achieved by a scheme formating the simulation output into three data blocks which has the priority data triply redundant in the first block in addition to having a retransmission priority on that first block when it is received in error.

Credeur, L.↗

Some Improvements in Utilization of Flash Memory Devices

Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.

Gender, Thomas K.↗

Optical communication with laser diode arrays

The performance of a direct-detection optical communication system in which the laser transmitter sends short optical pulses of selected nonoverlapping center frequencies is analysed. This modulation format, in which a single light pulse is sent in one of M time slots at one of N optical center frequencies, is referred to as color coded optical pulse position modulation (CCPPM). The optimum energy-efficiency of this system, as measured by the channel capacity in nats per photon, exceeds that of ordinary optical pulse position modulation which uses a pulsed laser of fixed optical frequency. Reliable communication at optimal energy efficiency is easily achieved through the use of modest block length Reed-Solomon codes with the code words represented as CCPPM symbols.

Davidson, F.↗

Software reliability through fault-avoidance and fault-tolerance

Accomplishments in the following research areas are summarized: structure based testing, reliability growth, and design testability with risk evaluation; reliability growth models and software risk management; and evaluation of consensus voting, consensus recovery block, and acceptance voting. Four papers generated during the reporting period are included as appendices.

Vouk, Mladen A.↗

Neural network applications in telecommunications

Neural network capabilities include automatic and organized handling of complex information, quick adaptation to continuously changing environments, nonlinear modeling, and parallel implementation. This viewgraph presentation presents Bellcore work on applications, learning chip computational function, learning system block diagram, neural network equalization, broadband access control, calling-card fraud detection, software reliability prediction, and conclusions.

Alspector, Joshua↗

Systems Engineering and Reusable Avionics

One concept for future space flights is to construct building blocks for a wide variety of avionics systems. Once a unit has served its original purpose, it can be removed from the original vehicle and reused in a similar or dissimilar function, depending on the function blocks the unit contains. For example: Once a lunar lander has reached the moon's surface, an engine controller for the Lunar Decent Module would be removed and used for a lunar rover motor control unit or for a Environmental Control Unit for a Lunar Habitat. This senior design project included the investigation of a wide range of functions of space vehicles and possible uses. Specifically, this includes: (1) Determining and specifying the basic functioning blocks of space vehicles. (2) Building and demonstrating a concept model. (3) Showing high reliability is maintained. The specific implementation of this senior design project included a large project team made up of Systems, Electrical, Computer, and Mechanical Engineers/Technologists. The efforts were made up of several sub-groups that each worked on a part of the entire project. The large size and complexity made this project one of the more difficult to manage and advise. Typical projects only have 3-4 students, but this project had 10 students from five different disciplines. This paper describes the difference of this large project compared to typical projects, and the challenges encountered. It also describes how the systems engineering approach was successfully implemented so that the students were able to meet nearly all of the project requirements.

Conrad, James M.↗

Software reliability through fault-avoidance and fault-tolerance

Twenty independently developed but functionally equivalent software versions were used to investigate and compare empirically some properties of N-version programming, Recovery Block, and Consensus Recovery Block, using the majority and consensus voting algorithms. This was also compared with another hybrid fault-tolerant scheme called Acceptance Voting, using dynamic versions of consensus and majority voting. Consensus voting provides adaptation of the voting strategy to varying component reliability, failure correlation, and output space characteristics. Since failure correlation among versions effectively reduces the cardinality of the space in which the voter make decisions, consensus voting is usually preferable to simple majority voting in any fault-tolerant system. When versions have considerably different reliabilities, the version with the best reliability will perform better than any of the fault-tolerant techniques.

Vouk, Mladen A.↗

Reliable Transport over SpaceWire for James Webb Space Telescope (JWST) Focal Plane Electronics (FPE) Network

NASA's James Webb Space Telescope (JWST) faces difficult technical and budgetary challenges to overcome before it is scheduled launch in 2010. The Integrated Science Instrument Module (ISIM), shares these challenges. The major challenge addressed in this paper is the data network used to collect, process, compresses and store Infrared data. A total of 114 Mbps of raw information must be collected from 19 sources and delivered to the two redundant data processing units across a twenty meter deployed thermally restricted interface. Further data must be transferred to the solid-state recorder and the spacecraft. The JWST detectors are kept at cryogenic temperatures to obtain the sensitivity necessary to measure faint energy sources. The Focal Plane Electronics (FPE) that sample the detector, generate packets from the samples, and transmit these packets to the processing electronics must dissipate little power in order to help keep the detectors at these cold temperatures. Separating the low powered front-end electronics from the higher-powered processing electronics, and using a simple high-speed protocol to transmit the detector data minimize the power dissipation near the detectors. Low Voltage Differential Signaling (LVDS) drivers were considered an obvious choice for physical layer because of their high speed and low power. The mechanical restriction on the number cables across the thermal interface force the Image packets to be concentrated upon two high-speed links. These links connect the many image packet sources, Focal Plane Electronics (FPE), located near the cryogenic detectors to the processing electronics on the spacecraft structure. From 12 to 10,000 seconds of raw data are processed to make up an image, various algorithms integrate the pixel data Loss of commands to configure the detectors as well as the loss of science data itself may cause inefficiency in the use of the telescope that are unacceptable given the high cost of the observatory. This combination of requirements necessitates a redundant, fault tolerant, high- speed, low mass, low power network with a low Bit error Rate(1E-9- 1E-12). The ISIM systems team performed many studies of the various network architectures that meeting these requirements. The architecture selected uses the Spacewire protocol, with the addition of a new transport and network layer added to implement end-to-end reliable transport. The network and reliable transport mechanism must be implemented in hardware because of the high average information rate and the restriction on the ability of the detectors to buffer data due to power and size restrictions. This network and transport mechanism was designed to be compatible with existing Spacewire links and routers so that existing equipment and designs may be leveraged upon. The transport layer specification is being coordinated with European Space Agency (ESA), Spacewire Working Group and the Consultative Committee for Space Data System (CCSDS) PlK Standard Onboard Interface (SOIF) panel, with the intent of developing a standard for reliable transport for Spacewire. Changes to the protocol presented are likely since negotiations are ongoing with these groups. A block of RTL VHDL that implements a multi-port Spacewire router with an external user interface will be developed and integrated with an existing Spacewire Link design. The external user interface will be the local interface that sources and sinks packets onto and off of the network (Figure 3). The external user interface implements the network and transport layer and handles acknowledgements and re-tries of packets for reliable transport over the network. Because the design is written in RTL, it may be ported to any technology but will initially be targeted to the new Actel Accelerator series (AX) part. Each link will run at 160 Mbps and the power will be about 0.165 Watt per link worst case in the Actel AX.

Rakow, Glenn↗

Preliminary Study of Capsule Recovery for the First Series of Project Mercury Orbital Flights

This report contains the results of a preliminary study of the search and. recovery operations required. for the safe and. expeditious return of the Mercury Recovery Capsule in the first series of orbital flights. The study is concerned primarily with the high-probability impact areas in the Atlantic Ocean. Emphasis is placed on safe recovery within reasonable time at least cost. A preliminary study of this nature is not able to provide final answers to all of the problems; the report instead constitutes a "first look" at the overall operation. Much of the report is therefore devoted to basic data, the building blocks from which recovery systems can be assembled and evaluated. These include the performance characteristics, reliability, and cost of the vehicles and equipment which may be used, and their compatibility with one another, with the capsule, and with the expected environment. The availability of vehicles and equipment has also been considered., although it is appreciated. that this may change from week to week where the forces are drawn from the military services. consideration of alternative vehicles, equipments, and systems, and their evaluation from the standpoint of effectiveness and. cost. While the equipment considered. is generally expected to be operational throughout 1960, consideration is also given to more advanced schemes which might effect reductions in recovery time, cost, or dependence upon the military forces.

Source record↗

IAPSA 2 small-scale system specification

The details of a hardware implementation of a representative small scale flight critical system is described using Advanced Information Processing System (AIPS) building block components and simulated sensor/actuator interfaces. The system was used to study application performance and reliability issues during both normal and faulted operation.

Cohen, Gerald C.↗

Advanced Health Management System for the Space Shuttle Main Engine

Pratt & Whitney Rocketdyne, Inc., in cooperation with NASA-Marshall Space Flight Center (MSFC), has developed a new Advanced Health Management System (AHMS) controller for the Space Shuttle Main Engine (SSME) that will increase the probability of successfully placing the shuttle into the intended orbit and increase the safety of the Space Transportation System (STS) launches. The AHMS is an upgrade o the current Block II engine controller whose primary component is an improved vibration monitoring system called the Real-Time Vibration Monitoring System (RTVMS) that can effectively and reliably monitor the state of the high pressure turbomachinery and provide engine protection through a new synchronous vibration redline which enables engine shutdown if the vibration exceeds predetermined thresholds. The introduction of this system required improvements and modification to the Block II controller such as redesigning the Digital Computer Unit (DCU) memory and the Flight Accelerometer Safety Cut-Off System (FASCOS) circuitry, eliminating the existing memory retention batteries, installation of the Digital Signal Processor (DSP) technology, and installation of a High Speed Serial Interface (HSSI) with accompanying outside world connectors. Test stand hot-fire testing along with lab testing have verified successful implementation and is expected to reduce the probability of catastrophic engine failures during the shuttle ascent phase and improve safely by about 23% according to the Quantitative Risk Assessment System (QRAS), leading to a safer and more reliable SSME.

Davidson, Matt↗

Maximum-likelihood soft-decision decoding of block codes using the A* algorithm

The A* algorithm finds the path in a finite depth binary tree that optimizes a function. Here, it is applied to maximum-likelihood soft-decision decoding of block codes where the function optimized over the codewords is the likelihood function of the received sequence given each codeword. The algorithm considers codewords one bit at a time, making use of the most reliable received symbols first and pursuing only the partially expanded codewords that might be maximally likely. A version of the A* algorithm for maximum-likelihood decoding of block codes has been implemented for block codes up to 64 bits in length. The efficiency of this algorithm makes simulations of codes up to length 64 feasible. This article details the implementation currently in use, compares the decoding complexity with that of exhaustive search and Viterbi decoding algorithms, and presents performance curves obtained with this implementation of the A* algorithm for several codes.

Ekroot, L.↗

Use of CCSDS and OSI Protocols on the Advanced Communications Technology Satellite

Although ACTS (Advanced Communications Technology Satellite) provides an almost error-free channel during much of the day and under most conditions, there are times when it is not suitable for reliably error-free data communications when operating in the uncoded mode. Because coded operation is not always available to every earth station, measures must be taken in the end system to maintain adequate throughput when transferring data under adverse conditions. The most effective approach that we tested to improve performance was the addition of an 'outer' Reed-Solomon code through use of CCSDS (Consultative Committee for Space Data Systems) GOS 2 (a forward error correcting code). This addition can benefit all users of an ACTS channel including those applications that do not require totally reliable transport, but it is somewhat expensive because additional hardware is needed. Although we could not characterize the link noise statistically (it appeared to resemble uncorrelated white noise, the type that block codes are least effective in correcting), we did find that CCSDS GOS 2 gave an essentially error-free link at BER's (bit error rate) as high as 6x10(exp -4). For users that demand reliable transport, an ARQ (Automatic Repeat Queuing) protocol such as TCP (Transmission Control Protocol) or TP4 (Transport Protocol, Class 4) will probably be used. In this category, it comes as no surprise that the best choice of the protocol suites tested over ACTS was TP4 using CCSDS GOS 2. TP4 behaves very well over an error-free link which GOS 2 provides up to a point. Without forward error correction, however, TP4 service begins to degrade in the 10(exp -7)-10(exp -6) range and by 4x10(exp -6), it barely gives any throughput at all. If Congestion Avoidance is used in TP4, the degradation is even more pronounced. Fortunately, as demonstrated here, this effect can be more than compensated for by choosing the Selective Acknowledgment option. In fact, this option can enable TP4 to deliver some throughput at error rates as high as 10(exp -5).

Chirieleison, Don↗