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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Intersymbol interference in digital communication systems, phase lock loop studies, channel simulator studies, binary signal sets for channel models, and shift register sequences
A system for analyzing asynchronous signals containing bits of information for ensuring the validity of said signals, by sampling each bit of information a plurality of times, and feeding the sampled pieces of bits of information into a sequence controlled is described. The sequence controller has a plurality of maps or programs through which the sampled pieces of bits are stepped so as to identify the particular bit of information and determine the validity and phase of the bit. The step in which the sequence controller is clocked is controlled by a storage register. A data decoder decodes the information fed out of the storage register and feeds such information to shift registers for storage.
New cyclic group codes of length 2(exp m) - 1 over (m - j)-bit symbols are introduced. These codes can be systematically encoded and decoded algebraically. The code rates are very close to Reed-Solomon (RS) codes and are much better than Bose-Chaudhuri-Hocquenghem (BCH) codes (a former alternative). The binary (m - j)-tuples are identified with a subgroup of the binary m-tuples which represents the field GF(2 exp m). Encoding is systematic and involves a two-stage procedure consisting of the usual linear feedback register (using the division or check polynomial) and a small table lookup. For low rates, a second shift-register encoding operation may be invoked. Decoding uses the RS error-correcting procedures for the m-tuple codes for m = 4, 5, and 6.
Charge coupled devices represent unique usage of the metal oxide semiconductor concept. These devices can sample an AC signal at the input, transfer charge proportional to this signal through the CCD shift register and then provide an output of the same frequency and shape as the input. The delay time between input and output is controlled by the CCD operating frequency and the number of stages in the shift resistor. This work is a reliability evaluation of the buried channel and surface channel CCD technologies. The constructions are analyzed, failure modes are described, and test results are reported.
Buried channel CCD shift registers were irradiated with 15 MeV neutrons. The irradiations were performed at 80 K and 295 K on operating devices with normal clocks and bias voltages applied. Dark current increased from the pre-irradiation value of 7 nA/sq cm to 1,600 nA/sq cm at 1 x 10 to the 13th power n/sq cm. The input gate threshold shift observed at 80K was minus 0.9 volts per 10 to the 13th power n/sq cm, a factor of 4 less than that predicted from a first order calculation of the equivalent ionization dose of neutrons in the oxide. Transfer efficiency measurements yielded a bulk electron trap creation rate for neutron irradiation of 14.0 cm to the minus 1 power at 295 K with a trap emission time constant of 25 microseconds.
A circuit for generating a sequence of pseudo random numbers, (A sub K). There is an exponentiator in GF(2 sup m) for the normal basis representation of elements in a finite field GF(2 sup m) each represented by m binary digits and having two inputs and an output from which the sequence (A sub K). Of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs (E sub K) of maximal length shift register of n stages. There is a switch having a pair of inputs and an output. The switch outputs is connected to the other of the two inputs of the exponentiator. One of the switch inputs is connected for initially receiving a primitive element (A sub O) in GF(2 sup m). Finally, there is a delay circuit having an input and an output. The delay circuit output is connected to the other of the switch inputs and the delay circuit input is connected to the output of the exponentiator. Whereby after the exponentiator initially receives the primitive element (A sub O) in GF(2 sup m) through the switch, the switch can be switched to cause the exponentiator to receive as its input a delayed output A(K-1) from the exponentiator thereby generating (A sub K) continuously at the output of the exponentiator. The exponentiator in GF(2 sup m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U(sub i) = 92(sup i) (for n(sub i) = 1 or 1 (for n(subi) = 0).
Design of two-cycle shift register using magnetic and electric parameters of ferrite-diode components
A power logic circuit, with bidirectional capability, is used to drive small loads in planned sequence. This is designed in the form of a shift register, with a reversible ring counter.
Perfect punctured cyclic codes from maximal shift register codes
Optimal cyclic group codes obtained by deleting or puncturing certain coordinates of maximal length shift register code
System theory - matrices, feedback control system, network synthesis, set theory, stability, shift registers, coding, theorem proving, polynomial roots, channels, and signal flow graphs
Digital comparator permits discrimination at accuracy of reference frequency. The compare circuit is a shift register element.
Alphameric/facsimile printer receives serial digital data in the form of a specified number of bits per group and prints it on thermally sensitive paper. A solid state shift-register memorizes the incoming serial digital data.
Coding theorems and shift register synthesis in relation to processing and transmission of information
Neurophysiological research on contrast detectors, and insight into neuronal closed loops from shift register theory
Adverse viewing effects caused by faulty photosensitive elements are eliminated. A linear maximal /or nonmaximal/ sequence generator gives a pseudorandom pulse train to selectively blank the display monitor during specified mosaic interrogation times. The outputs minimize the length of the required shift register generator.
Cross correlation of reverse maximal length shift register sequences
Minimization algorithm for switching systems synthesis, describing design of mass spectrometer curve function generator and autonomous shift register