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Results for “Single Event Upset (SEU)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.

Single Event Effects (SEE)↗
NASA NTRS1991

Prediction of error rates in dose-imprinted memories on board CRRES by two different methods

An analysis of the expected space radiation effects on the single event upset (SEU) properties of CMOS/bulk memories onboard the Combined Release and Radiation Effects Satellite (CRRES) is presented. Dose-imprint data from ground test irradiations of identical devices are applied to the predictions of cosmic-ray-induced space upset rates in the memories onboard the spacecraft. The calculations take into account the effect of total dose on the SEU sensitivity of the devices as the dose accumulates in orbit. Estimates of error rates, which involved an arbitrary selection of a single pair of threshold linear energy transfer (LET) and asymptotic cross-section values, were compared to the results of an integration over the cross-section curves versus LET. The integration gave lower upset rates than the use of the selected values of the SEU parameters. Since the integration approach is more accurate and eliminates the need for an arbitrary definition of threshold LET and asymptotic cross section, it is recommended for all error rate predictions where experimental sigma-versus-LET curves are available.

Brucker, G. J.↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
DOE OSTI2020

Radiation-hard miniature optical engine with high bandwidth

Future silicon trackers will be operated in an intense radiation environment and require large volumes of data to be transmitted off detector. In addition, the optical modules must be of low mass in order to limit multiple scattering and nuclear interactions that would degrade the overall performance of the detector. Here, we present a miniature optical engine that satisfies these constraints. The optical engine consists of an ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. Two ASICs are designed to operate a 12-channel VCSEL array at 1.28 or 5.12 Gb/s per channel, which yields a total data rate of up to 60 Gb/s. The core transistors are fabricated in a 65 nm CMOS process which enhance the radiation-hardness. Each channel contains equalizer (CTLE) and clock-data recovery circuits (CDR) so that the ASIC can restore the highly distorted electrical signal after propagating through several meters of cables of small diameter. The equalizer, CDR, and VCSEL driver are configured via a digital I 2 C chip interface with triple redundant memory to mitigate single event upset (SEU) effects. The bias and modulation currents are controlled by a digital-to-analog converter (DAC). We present the design of the circuit together with the results of the simulations and preliminary measurements.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm 2 /mg.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗
DOE OSTI2025

Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .

42 ENGINEERING↗
NASA NTRS1982

Single event upset sensitivity of low power Schottky devices

Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.

Price, W. E.↗
NASA NTRS1983

The physics of a single-event upset in integrated circuits: A review and critique of analytical models for charge collection

When an energetic particle (kinetic energy 0.5 MeV) originating from a radioactive decay or a cosmic ray transverse the active regions of semiconductor devices used in integrated circuit (IC) chips, it leaves along its track a high density electron hole plasma. The subsequent decay of this plasma by drift and diffusion leads to charge collection at the electrodes large enough in most cases to engender a false reading, hence the name single-event upset (SEU). The problem of SEU's is particularly severe within the harsh environment of Jupiter's radiation belts and constitutes therefore a matter of concern for the Galileo mission. The physics of an SEU event is analyzed in some detail. Owing to the predominance of nonlinear space charge effects and the fact that positive (holes) and negative (electrons) charges must be treated on an equal footing, analytical models for the ionized-charge collection and their corresponding currents as a function of time prove to be inadequate even in the simplest case of uniformly doped, abrupt p-n junctions in a one-dimensional geometry. The necessity for full-fledged computer simulation of the pertinent equations governing the electron-hole plasma therefore becomes imperative.

Vonroos, O.↗
NASA NTRS1983

Modeling of single-event upset in bipolar integrated circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.↗
NASA NTRS1984

Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

Zoutendyk, J. A.↗
NASA NTRS1986

Radiation Hardening of Computers

Single-event upsets reduced by use of oversize transistors. Computers made less susceptible to ionizing radiation by replacing bipolar integrated circuits with properly designed, complementary metaloxide-semiconductor (CMOS) circuits. CMOS circuit chips made highly resistant to single-event upset (SEU), especially when certain feedback resistors are incorporated. Redesigned chips also consume less power than original chips.

Nichols, D. K.↗
NASA NTRS1985

Cosmic ray simulation and testing program

Single event upset (SEU) and latchup vulnerabilities were determined for a number of parts of interest to NASA space programs. In cases where a threshold linear energy transfer (LET) for SEU could be measured, an upset rate in a low inclination Space Shuttle orbit was computed. The predicted upset rates are extremely low, except for the devices with LET thresholds below the geomagnetic cutoff for altitude and inclination of the Space Shuttle orbit. While some of the devices do exhibit latchup, the cross sections and threshold LETs are such that the risk associated with flying these devices in low, near equatorial orbits is small if not negligible.

Kolasinski, W. A.↗
NASA NTRS1985

Trends in parts susceptibility to single event upset from heavy ions

New test data have been combined with published data to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. These data have been arranged to exibit the SEU susceptibility of devices by function, technology, and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS1986

Trends in parts susceptibility to single event upset from heavy ions

New test data from the Jet Propulsion Laboratory (JPL), The Aerospace Corporation, Rockwell International (ANAHEIM) and IRT have been combined with published data of JPL and Aerospace to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. This data has been arranged to exhibit the SEU susceptibility of devices by function, technology and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS1987

Cosmic ray heavy ion LET mapping for aluminum, silicon, and tissue targets

Linear energy transfer (LET) values in aluminum, silicon, and tissue targets have been calculated for 31 galactic cosmic ray ion species in eight different units. The values are described for single event upset (SEU) effect assessments or radiobiological evaluations. The data are presented in graphical and tabular form.

Stassinopoulos, E. G.↗
NASA NTRS1986

1986 Annual Conference on Nuclear and Space Radiation Effects, 23rd, Providence, RI, July 21-23, 1986, Proceedings

The present conference on the effects of nuclear and space radiation on electronic hardware gives attention to topics in the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, electronic device radiation hardness assurance, SOI/SOS radiation effects, spacecraft charging and space radiation, IC radiation effects and hardening, single-event upset (SEU) phenomena and hardening, and EMP/SGEMP/IEMP phenomena. Specific treatments encompass the generation of interface states by ionizing radiation in very thin MOS oxides, the microdosimetry of meson energy deposited on 1-micron sites in Si, total dose radiation and engineering studies, plasma interactions with biased concentrator solar cells, the transient imprint memory effect in MOS memories, mechanisms leading to SEU, and the vaporization and breakdown of thin columns of water.

Ellis, Thomas D.↗
NASA NTRS1986

The Galileo single-event upset solution and risk assessment

The Galileo probe will be subject to radiation fields and energetic particle bombardment during its outward bound journey and in orbit around Jupiter and its moons. To avoid the occurrence and propagation of effects of single event upset (SEU) bit state changes induced by the bombardments attempts were made to harden the Galileo electronics against SEUs. The hazards are especially acute for Schottky diode and low-power Schottky TTL parts. The preventive action options which were scheduled are reviewed, noting the selection of CMOS chips as replacements for SEU-susceptible devices. The simulation and risk assessment that were performed to evaluate the potential success of the replacements are summarized, with emphasis on the data employed to ensure the accuracy of the assessments and the predicted effects of SEUs in the various Galileo subsystems.

Burdick, Garry M.↗