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At least 91 records · Page 5

Lamellar: A Rust-based Asynchronous Tasking and PGAS Runtime for High Performance Computing

Cybersecurity is one of the largest concerns in modern computing, impacting and dictating how governments, private corporations, and individuals interact with and live in an increasingly digital world. The NSA has recently released a memo [ 1] on “Software Memory Safety” where they highlight that both Microsoft and Google have stated around 70% of software vulnerabilities were due to memory safety issues. Although languages such as C and C++ provide freedom and flexibility with memory management, guaran- teeing safety falls mostly on the developer. The NSA recommends using “memory safe” languages whenever possible. In this paper we introduce Lamellar, an asynchronous tasking and PGAS HPC runtime written in Rust, one such "memory safe" language. We describe the entire Lamellar stack, from network interfaces to high- level abstractions such as distributed LamellarArrays and Active Messages. We conclude by showing comparable performance to legacy PGAS runtimes (e.g. OpenSHMEM) on a subset of the BALE kernel suite while maintaining strong memory safety principles.

HPC Software Systems, Rust Programming Language, P↗

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this paper, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

3-D NAND flash↗

A simulation study of carbon storage with active reservoir management

As part of the Integrated Midcontinent Stacked Carbon Storage Hub (IMSCS-Hub) project led by Battelle Memorial Institute, a study was conducted to determine the feasibility of storing carbon dioxide (CO 2 ) in the stacked saline rock formations of the Sleepy Hollow Field (SHF), located in Red Willow County, southern Nebraska. A series of CO 2 injection simulation scenarios, with and without active reservoir management (ARM; brine extraction), were evaluated to investigate the feasibility of storing 50+ million tonnes (Mt) of CO 2 . The results indicated CO 2 injection combined with ARM may enable permanent storage of 50+ Mt of CO 2 . The area of review (AOR), the area in which underground sources of drinking water (USDWs) might be endangered during CO 2 injection, was assessed for the simulation scenarios. In comparison to a case without ARM, brine extraction resulted in a much smaller AOR, covering an area of 42 square miles (108.8 km 2 ), roughly one-fourth the size of an AOR resulting from CO 2 injection without ARM. Our findings, presented in this paper, indicate that CO 2 injection with ARM can improve the CO 2 storage capacity of a geologic storage complex up to 100% while also reduce the rate of pressure buildup in the subsurface, resulting in a 75% reduction in AOR. This may help in lowering carbon capture and storage project costs, risks, and effort needed to meet monitoring requirements for a storage project.

54 ENVIRONMENTAL SCIENCES↗

Automatic inspection of program state in an uncooperative environment

Abstract The program state is formed by the values that the program manipulates. These values are stored in the stack, in the heap, or in static memory. The ability to inspect the program state is useful as a debugging or as a verification aid. Yet, there exists no general technique to insert inspection points in type‐unsafe languages such as C or C++. The difficulty comes from the need to traverse the memory graph in a so‐called uncooperative environment. In this article, we propose an automatic technique to deal with this problem. We introduce a static code transformation approach that inserts in a program the instrumentation necessary to report its internal state. Our technique has been implemented in LLVM. It is possible to adjust the granularity of inspection points trading precision for performance. In this article, we demonstrate how to use inspection points to debug compiler optimizations; to augment benchmarks with verification code; and to visualize data structures.

Magalhães, José Wesley de Souza↗

A set-associative, fault-tolerant cache design

The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.

Lamet, Dan↗

First Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and its Scalability for High-Density 3D Ferroelectric Capacitor Memory

In this article, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectricmetal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; V ) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for Vw/2 scheme and worsens the Vw/3 scheme as disturb increases to intolerable 2Vw/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (Cz).

42 ENGINEERING↗

arco (Assembled Resource-Constrained Optimization) [SWR-26-030]

Arco (Assembled Resource-Constrained Optimization) is a memory-smart optimization DSL and solver for LP and MIP problems on constrained hardware. The software is an optimization framework built around a KDL-based domain-specific language and a CLI compiler/solver. You write optimization models in .kdl files, and the arco CLI compiles, validates, inspects, and solves them. Language bindings (Python today, more planned) provide programmatic access to the same engine. Built for harder optimization problems on constrained resources, Arco is intentional about every allocation, careful with stack and heap behavior, and relentless about minimizing memory usage so more systems can run real workloads. Arco is built primarily for internal use within our organization. You are welcome to try it, but we make no guarantees about API stability or robustness at this stage

Sanchez Perez, Pedro Andres [National Laboratory o↗

Single-pass memory system evaluation for multiprogramming workloads

Modern memory systems are composed of levels of cache memories, a virtual memory system, and a backing store. Varying more than a few design parameters and measuring the performance of such systems has traditionally be constrained by the high cost of simulation. Models of cache performance recently introduced reduce the cost simulation but at the expense of accuracy of performance prediction. Stack-based methods predict performance accurately using one pass over the trace for all cache sizes, but these techniques have been limited to fully-associative organizations. This paper presents a stack-based method of evaluating the performance of cache memories using a recurrence/conflict model for the miss ratio. Unlike previous work, the performance of realistic cache designs, such as direct-mapped caches, are predicted by the method. The method also includes a new approach to the problem of the effects of multiprogramming. This new technique separates the characteristics of the individual program from that of the workload. The recurrence/conflict method is shown to be practical, general, and powerful by comparing its performance to that of a popular traditional cache simulator. The authors expect that the availability of such a tool will have a large impact on future architectural studies of memory systems.

Conte, Thomas M.↗

Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking

In this article, we study the limits of the number of capacitors and read history dependence in a 2T-nC ferroelectric random-access memory (FeRAM) cell, paving the way for its high-density integration toward hundreds of stacked layers. Through a comprehensive experimental and simulation study on the scaling behavior of the 2T-nC FeRAM architecture, we demonstrate: (i) successful fabrication of 2T-64C cells with robust memory operation and clearly distinguishable ‘0’ and ‘1’ states, even in 64- capacitor configurations; (ii) that the parasitic capacitance of the floating node originates predominantly from the linear component of the ferroelectric capacitor, and its impact on n-scaling—due to degraded sense margin—can be mitigated by floating unselected capacitors with enough TΩ isolation; (iii) that sharing write and read transistors among n capacitors introduces a read history dependence issue due to fluctuating floating node voltage (VFN); and (iv) that a proposed FN discharge scheme can effectively eliminate read-sequence dependence, at the cost of reduced read endurance.

36 MATERIALS SCIENCE↗

Precursor Analysis Report: SQL Slammer Worm Infection of Davis-Besse Nuclear Power Plant 2003

The SQL Slammer Worm Infection of Davis-Besse Nuclear Power Plant 2003 Precursor Analysis Report leverages publicly available information about Davis-Besse’s 2003 cyber attack and catalogs anomalous observables for each technique employed in the attack. This analysis is based upon the methodology of the Cybersecurity for the Operational Technology Environment (CyOTE) program. On 25 January 2003, the SQL Slammer worm infected more than 90% of vulnerable hosts and crashed the internet in 10 to 15 minutes, making it one of the fastest spreading worms in history. SQL Slammer is a fileless, memory-resident worm that remotely exploits a stack-based buffer overflow vulnerability on local hosts to intensively scan and rapidly self-propagate across the internet. The worm infected approximately 300,000 unpatched hosts running Microsoft Structured Query Language (SQL) Server 2000 or Microsoft Desktop Engine (MSDE) 2000 with SQL Server Resolution Service. The SQL Slammer worm indirectly infected FirstEnergy’s Davis-Besse nuclear power plant by first infecting a consultant’s company network server and then propagating through an external misconfigured connection into Davis-Besse’s site network. The infection caused major network congestion, slow performance, data overloads, and the inability of local hosts to communicate with each other, which eventually caused a loss of availability and a loss of view when the Safety Parameter Display System (SPDS) and Plant Process Computer (PPC) crashed. At the time of the infection, the plant was already offline, the digital monitoring systems had redundant analog backups, and the plant control and safety functions were not affected, so there were no concerns of a safety breach. However, this incident resulted in many lessons learned and spawned important discussions about cybersecurity’s role in nuclear safety and electric power reliability regulation, policy, and guidance. Researchers and analysts identified 10 unique techniques utilized during the attack with a total of 640 observables using MITRE ATT&CK® for Industrial Control Systems. The CyOTE program assesses observables accompanying techniques used prior to the triggering event to identify opportunities to detect malicious activity. If observables accompanying the attack techniques are perceived and investigated prior to the triggering event, earlier comprehension of malicious activity can take place. Eight of the identified techniques used during Davis-Besse cyber attack were precursors to the triggering event. Analysis identified 596 observables associated with these precursor techniques, 428 of which were assessed to have an increased likelihood of being perceived in the 331 days preceding the triggering event. The response and comprehension time could have been reduced if the observables had been identified earlier. The information gathered in this report contributes to a library of observables tied to a repository of artifacts, data sources, and technique detection references for practitioners and developers to support the comprehension of indicators of attack. Asset owners and operators can use these products if they experience similar observables or to prepare for comparable scenarios.

45 MILITARY TECHNOLOGY, WEAPONRY, AND NATIONAL DEF↗

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗

FLYING SERVING: On-the-Fly Parallelism Switching for Large Language Model Serving

Production LLM serving must simultaneously deliver high throughput, low latency, and sufficient context capacity under non-stationary traffic and mixed request requirements. Data parallelism (DP) maximizes throughput by running independent replicas, while tensor parallelism (TP) reduces per-request latency and pools memory for long-context inference. However, existing serving stacks typically commit to a static parallelism configuration at deployment; adapting to bursts, priorities, or long-context requests is often disruptive and slow. We present Flying Serving, a vLLM-based system that enables online DP-TP switching without restarting engine workers. Flying Serving makes reconfiguration practical by virtualizing the state that would otherwise force data movement: (i) a zero-copy Model Weights Manager that exposes TP shard views on demand, (ii) a KV Cache Adaptor that preserves request KV state across DP/TP layouts, (iii) an eagerly initialized Communicator Pool to amortize collective setup, and (iv) a deadlock-free scheduler that coordinates safe transitions under execution skew. Across three popular LLMs and realistic serving scenarios, Flying Serving improves performance by up to 4.79 × under high load and 3.47 × under low load while supporting latency- and memory-driven requests.

Gao, Shouwei [ORNL]↗

The shape recovery conditions for Fe–Mn–Si alloys: An interplay between martensitic transformation and plasticity

Highlights: • Fe15Mn5Si9Cr5Ni samples were rolled at 800 °C and annealed at 650 (C1) and 1000 °C (C2). • TEM analysis was performed. • High density of stacking faults and appropriate density of dislocation appears in C1. • Complex dislocation arrays due to plastic deformation are observed in C2. • Shape memory properties depend on the thermomechanical treatment. - Abstract: This work analyses the improvement of the shape memory properties of Fe-Mn-Si based alloys, and expands upon and deepens recently published developments concerning this topic. We prepared TEM specimens from a Fe-15Mn-5Si-9Cr-5Ni sheet rolled at 800 °C and annealed at 650 °C–92% shape recovery – and from another sheet annealed at 1000 °C–45% shape recovery. Here, we analyse the development of microstructure during the γ ↔ ε martensitic transformation and correlate it with the shape memory behaviour. Among the observed microstructural features, the introduction of complex dislocation arrays due to plastic deformation appears to be critical for shape memory development, since they can arrest the backward movement of Shockley partial dislocations over the original path. Tailoring the microstructure in order to introduce a high stacking-fault density accompanied by an appropriate dislocation density remains a key issue in the design of these kinds of functional materials.

36 MATERIALS SCIENCE↗

On the error probability of general trellis codes with applications to sequential decoding

An upper bound on the average probability of error for maximum-likelihood decoding of the ensemble of random L-branch binary trellis codes of rate R = 1/n with distinction between memory length and tail length is given. It is shown that the bound is independent of the length L of the information sequence if the memory length exceeds the tail length by a specified amount that depends on L. Sequential decoding simulations using the stack algorithm were conducted to test the dependence of the undetected error probability on tail length and memory length, and the results corroborated the theory.

Johannesson, R.↗

Giant Nonlinear Optical Response via Coherent Stacking of In-Plane Ferroelectric Layers

Thin ferroelectric materials hold great promise for compact nonvolatile memory and nonlinear optical and optoelectronic devices. Herein, an ultrathin in-plane ferroelectric material that exhibits a giant nonlinear optical effect, group-IV monochalcogenide SnSe, is reported. Nanometer-scale ferroelectric domains with ≈90°/270° twin boundaries or ≈180° domain walls are revealed in physical-vapor-deposited SnSe by lateral piezoresponse force microscopy. Atomic structure characterization reveals both parallel and antiparallel stacking of neighboring van der Waals ferroelectric layers, leading to ferroelectric or antiferroelectric ordering. Ferroelectric domains exhibit giant nonlinear optical activity due to coherent enhancement of second-harmonic fields and the as-resulted second-harmonic generation was observed to be 100 times more intense than monolayer WS 2 . This work demonstrates in-plane ferroelectric ordering and giant nonlinear optical activity in SnSe, which paves the way for applications in on-chip nonlinear optical components and nonvolatile memory devices.

36 MATERIALS SCIENCE↗

Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking, in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Simulating an aerospace multiprocessor

The paper describes a simulator which was used to evaluate the architecture of an aerospace multiprocessor. The simulator models interactions among the processors, memories, the central data bus, and a possible 'job stack'. Special features of the simulator are discussed, including the use of explicitly coded and individually distinguishable 'job models' instead of a statistically defined 'job mix' and a specialized Job Model Definition Language to automate the detailed coding of the models. Some results are presented which show that when the simulator was employed in conjunction with queuing theory and Markov-process analysis, more insight into system behavior was obtained than would have been with any one technique alone.

Mallach, E. G.↗

High Density Memory Based on Quantum Device Technology

We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

vanderWagt, Paul↗