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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1989

Universal test fixture for monolithic mm-wave integrated circuits calibrated with an augmented TRD algorithm

The design and evaluation of a novel fixturing technique for characterizing millimeter wave solid state devices is presented. The technique utilizes a cosine-tapered ridge guide fixture and a one-tier de-embedding procedure to produce accurate and repeatable device level data. Advanced features of this technique include nondestructive testing, full waveguide bandwidth operation, universality of application, and rapid, yet repeatable, chip-level characterization. In addition, only one set of calibration standards is required regardless of the device geometry.

Romanofsky, Robert R.↗
NASA NTRS1989

Optical Firmware

Data-processing system exploits high speeds inherent in optical elements. Instruction sets for different computer operations reside on different external memory chips. Laser diodes activated for each operation generate light, reflected by holographic optical element to designated receptors in arithmetic and logic unit. Pattern of light beams embodies instruction set at given instant. With potential ability to reprogram in real time, conceptual system applicable to task-driven programming or artificial intelligence.

Bergman, Larry A.↗
DOE OSTI2025

Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)

Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.

Quinn, Adam [Fermilab]↗
NASA NTRS1991

High resolution decoding of Multi-Anode Microchannel Array detectors

The Multi-Anode Microchannel Array (MAMA) is a photon counting detector which utilizes a photocathode for photon to electron conversion, a microchannel plate (MCP) for signal amplification and a proximity focused anode array for position sensitivity. The detector electronics decode the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. A new algorithm incorporated into a CMOS Application Specific Integrated Circuit (ASIC) decoder which improves the pixel spatial resolution is described. The new algorithm does not degrade the detector throughput and does not require any modifications to the detector tube. The standard MAMA detector has a pixel size of 25 x 25 square microns, but with the new decoder circuit the pixel size is reduced to 12.5 x 12.5 square microns. We have built the first set of decode electronics utilizing the new ASIC chips and report here on the first imaging tests of this system.

Kasle, David B.↗
NASA NTRS2018

The Wide-Field Spatio-Spectral Interferometer: System Overview, Data Synthesis and Analysis

The Wide-field Imaging Interferometry Testbed (WIIT) is a double Fourier (DF) interferometer operating at optical wavelengths, and provides data that are highly representative of those from a space-based far-infrared interferometer like SPIRIT. We have used the testbed to observe both geometrically simple and astronomically representative test scenes. Here we present an overview of the astronomical importance of high angular resolution at the far infrared, followed by the description of the optical set-up of WIIT, including the source simulator CHIP (Calibrated Hyperspectral Image Projector). We describe our synthesis algorithms used in the reconstruction of the input test scenes via a simulation of the most recent measurements. The updated algorithms, which include instruments artifacts that allow the synthesis of DF experimental data, are presented and the most recent results analyzed.

Juanola-Parramon, Roser↗
NASA NTRS2003

Cascade Back-Propagation Learning in Neural Networks

The cascade back-propagation (CBP) algorithm is the basis of a conceptual design for accelerating learning in artificial neural networks. The neural networks would be implemented as analog very-large-scale integrated (VLSI) circuits, and circuits to implement the CBP algorithm would be fabricated on the same VLSI circuit chips with the neural networks. Heretofore, artificial neural networks have learned slowly because it has been necessary to train them via software, for lack of a good on-chip learning technique. The CBP algorithm is an on-chip technique that provides for continuous learning in real time. Artificial neural networks are trained by example: A network is presented with training inputs for which the correct outputs are known, and the algorithm strives to adjust the weights of synaptic connections in the network to make the actual outputs approach the correct outputs. The input data are generally divided into three parts. Two of the parts, called the "training" and "cross-validation" sets, respectively, must be such that the corresponding input/output pairs are known. During training, the cross-validation set enables verification of the status of the input-to-output transformation learned by the network to avoid over-learning. The third part of the data, termed the "test" set, consists of the inputs that are required to be transformed into outputs; this set may or may not include the training set and/or the cross-validation set. Proposed neural-network circuitry for on-chip learning would be divided into two distinct networks; one for training and one for validation. Both networks would share the same synaptic weights.

Duong, Tuan A.↗
DOE OSTI2021

Single photon sources with near unity collection efficiencies by deterministic placement of quantum dots in nanoantennas

Deterministic coupling between photonic nodes in a quantum network is an essential step toward implementing various quantum technologies. The omnidirectionality of free-standing emitters, however, makes this coupling highly inefficient, in particular if the distant nodes are coupled via low numerical aperture (NA) channels such as optical fibers. This limitation requires placing quantum emitters in nanoantennas that can direct the photons into the channels with very high efficiency. Moreover, to be able to scale such technologies to a large number of channels, the placing of the emitters should be deterministic. In this work, we present a method for directly locating single free-standing quantum emitters with high spatial accuracy at the center of highly directional bullseye metal–dielectric nanoantennas. We further employ non-blinking, high quantum yield colloidal quantum dots for on-demand single-photon emission that is uncompromised by instabilities or non-radiative exciton recombination processes. Taken together, this approach results in a record-high collection efficiency of 85% of the single photons into a low NA of 0.5, setting the stage for efficient coupling between on-chip, room temperature nanoantenna-emitter devices and a fiber or a remote free-space node without the need for additional optics.

36 MATERIALS SCIENCE↗
DOE OSTI2022

kynema-fmb [SWR-23-07]

Kynema-FMB (FKA: Kynema) is an open-source performance portable flexible multibody (FMB) dynamics solver designed for time-domain simulations. While originally tailored for wind turbine structural dynamics, the formulation and implementation are those of a general flexible-multidbody dynamics solver that can readily be applied to a wide range of systems. Kynema was designed with a narrow focus, namely to provide a lightweight, fast, accurate FMD solver for coupling to computational-fluid-dynamics (CFD) codes, especially the CFD codes in the Kynema suite, for fluid-structure-interaction (FSI) simulations. Kynema-FMB is equipped to model systems that can be represented as a collection of beams and rigid bodies that are connected through constraints. Degrees of freedom are defined in the inertial/global frame of reference and include displacements and rotations (formally as rotation matrices, but stored as quaternions). The underlying formulation is built on a Lie-group time integrator designed for index-3 differential-algebraic equations, which is second-order accurate in time (Bruls et al., 2012). Beam models are based on geometrically exact beam theory and are discretized as high-order spectral finite elements similar to those in BeamDyn (Wang et al., 2017). The governing equations for a FMD system like a wind turbine constitute a highly nonlinear system of constrained partial-differential equations. Kynema-FMB uses analytical Jacobians in the nonlinear-system solves in each time step. Linear systems use sparse storage and several third-party sparse-linear-system solvers are enabled. Ill conditioning of linear systems is mitigated with preconditioning described in Bottasso et al, 2008. Kynema-FMB is integrated with a simple open-source controller (ROSCO). There is an application programming interface (API) for coupling to geometry-resolved CFD (like that in Sharma et al., 2023) and actuator-force CFD (like that in Kuhn et al., 2025). In the latter, for actuator-line models, Kynema-FMB includes an internal blade-element solver that depends on user-provided lookup tables for coefficients of lift and drag, i.e., aerodynamic polars. Kynema-FMB is written in C++ and leverages Kokkos and Kokkos-Kernels (KokkosEcosystem) as its performance portability layer enabling simulations on both CPU and GPU systems. The repository is equipped with extensive automated testing at the unit and regression/system levels. The following describes the high-level development objectives conceived for Kynema: *Kynema will follow modern software development best practices, including test-driven development (TDD), version control, hierarchical automated testing, and continuous integration (CI) for a robust development environment. *The core data structures are memory efficient and enable vectorization and parallelization at multiple levels. *Data structures are data-oriented to exploit methods for accelerated computing including high utilization of chip resources (e.g., single instruction multiple data (SIMD) instruction sets) and parallelization using GP-GPUs. *The computational algorithms incorporate robust open-source libraries for mathematical operations, resource allocation, and data management. *The API design considers multiple stakeholder needs and ensure integration with existing and future ecosystems for data science, machine learning, and AI. *Kynema-FMB is written in modern C++ and leverages Kokkos as its performance-portability library with inspiration from the kynema stack.

Sprague, MichaelA.↗
NASA NTRS1985

The 1.2 micron CMOS technology

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.↗
DOE OSTI2022

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor

Advanced, superscalar microprocessors (μP) are highly susceptible to wear-out failures because of their highly complex, densely packed circuit structure and extreme operational frequencies. Although many types of fault detection and mitigation strategies have been proposed, none have addressed the specific problem of detecting faults that lead to information leakage events on I/O channels of the μP. Information leakage can be defined very generally as any type of output that the executing program did not intend to produce. In this work, we restrict this definition to output that represents a security concern, and in particular, to the leakage of plaintext or encryption keys, and propose a counter-based countermeasure to detect faults that cause this type of leakage event. Fault injection (FI) experiments are carried out on two RISC-V microprocessors emulated as soft cores on a Xilinx multi-processor System-on-chip (MPSoC) FPGA. The μP designs are instrumented with a set of counters that records the number of transitions that occur on internal nodes. The transition counts are collected from all internal nodes under both fault-free and faulty conditions, and are analyzed to determine which counters provide the highest fault coverage and lowest latency for detecting leakage faults. We show that complete coverage of all leakage faults is possible using only a single counter strategically placed within the branch compare logic of the μPs.

42 ENGINEERING↗
NASA NTRS2000

RF Single Electron Transistor Readout Amplifiers for Superconducting Astronomical Detectors for X-Ray to Sub-mm Wavelengths

We report progress on using a new type of amplifier, the Radio-Frequency Single-Electron Transistor (RF-SET), to develop multi-channel sensor readout systems for fast and sensitive readout of high impedance cryogenic photodetectors such as Superconducting Tunnel Junctions and Single Quasiparticle Photon Counters. Although cryogenic, these detectors are desirable because of capabilities not other-wise attainable. However, high impedances and low output levels make low-noise, high-speed readouts challenging, and large format arrays would be facilitated by compact, low-power, on-chip integrated amplifiers. Well-suited for this application are RF-SETs, very high performance electrometers which use an rf readout technique to provide 100 MHz bandwidth. Small size, low power, and cryogenic operation allow direct integration with detectors, and using multiple rf carrier frequencies permits simultaneous readout of 20-50 amplifiers with a common electrical connection. We describe both the first 2-channel demonstration of this wavelength division multiplexing technique for RF-SETs, and Charge-Locked-Loop operation with 100 kHz of closed-loop bandwidth.

Stevenson, Thomas↗
DOE OSTI2026

Directional dependence of equilibrated TLD-400 chips in multiple radiation fields

Fielding of thermoluminescent dosimeters (TLDs) for measurement of photon radiation dose in experiments is the standard practice for γ-irradiation facilities, pulsed power x-ray facilities, and reactor facilities at Sandia National Laboratories (SNL). Due to the high-dose experimental conditions and the mixed ( 1 n, γ) fields in these facilities, SNL radiation metrologists have historically used CaF 2 :Mn TLDs (also known as TLD-400). Recent inquiries to the radiation metrology staff have raised concerns that the aluminum-equilibrated TLD-400 chips may exhibit a directionally dependent response. The metrologists were asked whether the dose measured by the chip may be impacted by the angle of incidence on the equilibrated TLD. To provide a thorough answer to this query, a set of adjoint Monte Carlo radiation transport calculations was performed for three different equilibrated TLDs as well as bare TLD chips using the Integrated Tiger Series (ITS) code. The key feature of the adjoint calculations performed in this study is that each photon escaping the modeled geometry was tallied into angular bins to provide information on both the energy and angular dependence of the equilibrated chip. After the adjoint Monte Carlo calculations were completed, the resulting energy-dependent response function for each angular bin was convolved with multiple photon energy spectra representing various radiation facilities at SNL. The radiation facilities selected for analysis span a range of photon energies from approximately 1 keV up to approximately 20 MeV. Thus, the presented results are applicable to a wide variety of radiation facilities around the world. Although the bare TLD-400 chip was expected to display the largest variation due to the photon angle of impact on the dosimeter, the dosimeter with the thinnest aluminum equilibrator (SNL thin equilibrated TLD-400) was determined to have the biggest differential between the impact angle with the maximum dose ( D max ) and the impact angle with the minimum dose ( D min ). However, the SNL normal equilibrated TLD-400 chip demonstrated a dramatic reduction in that differential between maximum and minimum dose angles. The reduction in this differential is one of the dominant factors in experimenters’ choice to field these dosimeters at SNL radiation facilities. The results from the PNNL (Hanford) energy-flattening field capsule are consistent with the previous publications. The differential dose responses due to the photon impact angle indicate that experimenters should strive to field their TLD-400 dosimeters in a consistent manner to avoid additional uncertainty in the measurements based on dosimeter orientation.

Adjoint radiation transport↗
DOE OSTI2023

A user-friendly plug-and-play cyclic olefin copolymer-based microfluidic chip for room-temperature, fixed-target serial crystallography

Over the past two decades, serial X-ray crystallography has enabled the structure determination of a wide range of proteins. With the advent of X-ray free-electron lasers (XFELs), ever-smaller crystals have yielded high-resolution diffraction and structure determination. A crucial need to continue advancement is the efficient delivery of fragile and micrometre-sized crystals to the X-ray beam intersection. This paper presents an improved design of an all-polymer microfluidic `chip' for room-temperature fixed-target serial crystallography that can be tailored to broadly meet the needs of users at either synchrotron or XFEL light sources. The chips are designed to be customized around different types of crystals and offer users a friendly, quick, convenient, ultra-low-cost and robust sample-delivery platform. Compared with the previous iteration of the chip [Gilbile et al. (2021), Lab Chip , 21 , 4831–4845], the new design eliminates cleanroom fabrication. It has a larger imaging area to volume, while maintaining crystal hydration stability for both in situ crystallization or direct crystal slurry loading. Crystals of two model proteins, lysozyme and thaumatin, were used to validate the effectiveness of the design at both synchrotron (lysozyme and thaumatin) and XFEL (lysozyme only) facilities, yielding complete data sets with resolutions of 1.42, 1.48 and 1.70 Å, respectively. Overall, the improved chip design, ease of fabrication and high modifiability create a powerful, all-around sample-delivery tool that structural biologists can quickly adopt, especially in cases of limited sample volume and small, fragile crystals.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2025

The AMACStar ASIC for the HL-LHC ATLAS ITk Strip detector: design, verification, testing, and quality assurance

For the high-luminosity upgrade to the LHC (HL-LHC), the ATLAS detector at CERN requires an all-new inner detector, the Inner Tracker (ITk). The ITk Strip subdetector is made up of silicon modules, which include three types of radiation-hard ASICs. One of these is the Autonomous Monitor and Control (AMAC). The AMAC is manufactured by Global Foundries using 130 nm CMOS8RF DM technology and is approximately 3 by 5 mm in size. This ASIC autonomously monitors the temperatures, voltages, and currents in the module components while controlling critical values in order to prevent these quantities from reaching dangerous levels. The final design, AMACStar, was verified, tested, and ensured to perform all necessary functions. A quality control procedure using an in-house probe station set-up was developed in order to ensure that every individual chip on each wafer of AMACStars required by the ITk Strip project met performance requirements. The average per wafer yield of usable AMACStars is 92.33%, exceeding the design-specific 90% yield estimated for project costing. This estimate was based on actual yields for similar designs in this process.

Analogue electronic circuits↗
NASA NTRS1990

Feasibility study, software design, layout and simulation of a two-dimensional fast Fourier transform machine for use in optical array interferometry

The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.

Boriakoff, Valentin↗
NASA NTRS1999

System-on-Chip Data Processing and Data Handling Spaceflight Electronics

This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.

Kleyner, I.↗