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NASA NTRS1999

System-on-Chip Data Processing and Data Handling Spaceflight Electronics

This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.

Kleyner, I.↗

NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗

NASA NTRS2002

Heavy Ion Transient Characterization of a Photobit Hardened-by-Design Active Pixel Sensor Array

This paper presents heavy ion data on the single event transient (SET) response of a Photobit active pixel sensor (APS) four quadrant test chip with different radiation tolerant designs in a standard 0.35 micron CMOS process. The physical design techniques of enclosed geometry and P-channel guard rings are used to design the four N-type active photodiode pixels as described in a previous paper. Argon transient measurements on the 256 x 256 chip array as a function of incident angle show a significant variation in the amount of charge collected as well as the charge spreading dependent on the pixel type. The results are correlated with processing and design information provided by Photobit. In addition, there is a large degree of statistical variability between individual ion strikes. No latch-up is observed up to an LET of 106 MeV/mg/sq cm.

Marshall, Paul W.↗

NASA NTRS2006

Microgravity and Immunity: Changes in Lymphocyte Gene Expression

Earlier studies had shown that modeled and true microgravity (MG) cause multiple direct effects on human lymphocytes. MG inhibits lymphocyte locomotion, suppresses polyclonal and antigen-specific activation, affects signal transduction mechanisms, as well as activation-induced apoptosis. In this study we assessed changes in gene expression associated with lymphocyte exposure to microgravity in an attempt to identify microgravity-sensitive genes (MGSG) in general and specifically those genes that might be responsible for the functional and structural changes observed earlier. Two sets of experiments targeting different goals were conducted. In the first set, T-lymphocytes from normal donors were activated with antiCD3 and IL2 and then cultured in 1g (static) and modeled MG (MMG) conditions (Rotating Wall Vessel bioreactor) for 24 hours. This setting allowed searching for MGSG by comparison of gene expression patterns in zero and 1 g gravity. In the second set - activated T-cells after culturing for 24 hours in 1g and MMG were exposed three hours before harvesting to a secondary activation stimulus (PHA) thus triggering the apoptotic pathway. Total RNA was extracted using the RNeasy isolation kit (Qiagen, Valencia, CA). Affymetrix Gene Chips (U133A), allowing testing for 18,400 human genes, were used for microarray analysis. In the first set of experiments MMG exposure resulted in altered expression of 89 genes, 10 of them were up-regulated and 79 down-regulated. In the second set, changes in expression were revealed in 85 genes, 20 were up-regulated and 65 were down-regulated. The analysis revealed that significant numbers of MGS genes are associated with signal transduction and apoptotic pathways. Interestingly, the majority of genes that responded by up- or down-regulation in the alternative sets of experiments were not the same, possibly reflecting different functional states of the examined T-lymphocyte populations. The responder genes (MGSG) might play an essential role in adaptation to MG and/or be responsible for pathologic changes encountered in Space and thus represent potential targets for molecular-based countermeasures

Risin, D.↗

NASA NTRS2010

SEU/SET Tolerant Phase-Locked Loops

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

Shuler, Robert L., Jr.↗

NASA NTRS1986

Phase-Locked Laser Array With Nonuniform Spacing

To obtain phase-locked array that reliably produces single far-field lobe, configuration includes lasing stripes not placed on regular centers but located in regular way with nonuniform centers (i.e., with spacing determined by some function). Alternatively, lasing stripes placed on set of periodic arrays with different stripe-to-stripe centers interlaced onto single chip or placed in structure in which stripe-to-stripe spacing is random or pseudorandom. Monolithic, phase-locked, semiconductor-laser array design produces output laser beam comprising substantially single lobe.

Ackley, D. E.↗

NASA NTRS1983

Programming substructure computations for elliptic problems on the CHiP system

A number of studies have been conducted with the aim to apply parallel computation to problems associated with solving finite element equations arising in structural mechanics and fluid dynamics. These studies have provided many important results. The present investigation is concerned with a set of experiments designed to test two ideas, including configurability and substructuring. The considered algorithms and tests are intended for implementation on the Configurable, Highly Parallel (CHiP) family of architecture described by Snyder (1982). The ChiP computer is composed of homogeneous processing elements (PEs) placed at regular intervals in a lattice of programmable switches. Two examples of the role of configurability and substructuring for simple iterative algorithms are considered, giving attention to conjugate gradient iterations, and tridiagonal systems of equations.

Gannon, D.↗

NASA NTRSDate not supplied

Performance Assessment of LunaNet’s Augmented Forward Signal

LunaNet provides a common set of interoperable specifications for communication and position, navigation and time (PNT) services and interfaces soon to be implemented in lunar vicinity. The LunaNet Interoperability Specification (LNIS) provides the design for the GNSS-like Augmented Forward Signal (AFS), which enables orbiting and surface users in lunar space, such as Artemis, to estimate their position, velocity, and time. The specification of AFS defines two orthogonal signal components on a single carrier: the in-phase component (AFS-I), a lower-chip-rate data channel tailored for applications where low SWaP (Size, Weight, and Power) is critical (e.g., IoT devices or search and rescue), and the quadrature component (AFS-Q), a high-chip-rate data-less pilot signal for high-precision, robust lunar navigation and positioning applications. An initial description of AFS was provided in [1], with initial analysis results shown in [2] and [3] and the current signal in space description provided in [4]. As part of NASA's Lunar Communication Relay and Navigation Systems (LCRNS) project, this work expands upon the initial analysis results and proposes a new expanded set of AFS-Q spreading codes that exceed the cross-correlation and autocorrelation sidelobe performance of L1C and other GNSS signals, while providing additional expansion capabilities for future provider satellites. A set of 420 codes was selected from a Weil-based code derived from the prime number 10247, which is larger than the 10243 prime number used to derive Beidou’s B1C Weil sequences. Both the initial set of 210 codes and the expanded set of 420 codes are shown to provide the best cross-correlation of any 10230-chip satellite navigation codes. The performance is demonstrated for hierarchical sets of spreading codes optimized and organized in sets of 30 codes. The new codes were developed using an optimization approach and correlation methodology described in [5]. The work also compares LunaNet’s AFS to terrestrial GNSS signals in terms of acquisition, tracking, and data demodulation performance. Performance is evaluated for receivers that only track the 1.023 MCPS data channel spreading code for low SWaP IoT use cases, as well as for receivers that track both the 1.023 MCPS data channel and the 5.115 MCPS pilot channel spreading code for high-performance use cases. Performance is assessed in the presence of interference and thermal noise. The analysis is performed in terms of expected operating conditions on the lunar surface. Several unique flexibility aspects of the augmented forward signal are described, including the use of the Q channel’s secondary and tertiary codes to enable variable coherent integrations during acquisition. This is compared to GNSS signals such as L5/E5 and MBOC in terms of achievable processing gain for interference mitigation versus acquisition complexity. The work details acquisition and tracking techniques used to optimally acquire and track the primary, secondary, and tertiary codes on the Q channel, as well as acquisition of the I channel spreading code. Acquisition of the 8 ms Q channel spreading code is also compared to joint acquisition of the I and Q channel primary codes in noise and interference environments.

LCRNS↗

NASA NTRS1984

Finite element computation on nearest neighbor connected machines

Research aimed at faster, more cost effective parallel machines and algorithms for improving designer productivity with finite element computations is discussed. A set of 8 boards, containing 4 nearest neighbor connected arrays of commercially available floating point chips and substantial memory, are inserted into a commercially available machine. One-tenth Mflop (64 bit operation) processors provide an 89% efficiency when solving the equations arising in a finite element problem for a single variable regular grid of size 40 by 40 by 40. This is approximately 15 to 20 times faster than a much more expensive machine such as a VAX 11/780 used in double precision. The efficiency falls off as faster or more processors are envisaged because communication times become dominant. A novel successive overrelaxation algorithm which uses cyclic reduction in order to permit data transfer and computation to overlap in time is proposed.

Mcaulay, A. D.↗

NASA NTRSDate not supplied

Performance Assessment of LunaNet’s Augmented Forward Signal

LunaNet provides a common set of interoperable specifications for communication and position, navigation and time (PNT) services and interfaces soon to be implemented in lunar vicinity. The LunaNet Interoperability Specification (LNIS) provides the design for the GNSS-like Augmented Forward Signal (AFS), which enables orbiting and surface users in lunar space, such as Artemis, to estimate their position, velocity, and time. The specification of AFS defines two orthogonal signal components on a single carrier: the in-phase component (AFS-I), a lower-chip-rate data channel tailored for applications where low SWaP (Size, Weight, and Power) is critical (e.g., IoT devices or search and rescue), and the quadrature component (AFS-Q), a high-chip-rate data-less pilot signal for high-precision, robust lunar navigation and positioning applications. An initial description of AFS was provided in LNIS 2023, with initial analysis results shown in Dafesh 2024 and Dafesh 2025, and the current signal in space description provided in LNIS 2025. As part of NASA's Lunar Communication Relay and Navigation Systems (LCRNS) project, this work expands upon the initial analysis results and proposes a new expanded set of AFS-Q spreading codes that exceed the cross-correlation and autocorrelation sidelobe performance of L1C and other GNSS signals, while providing additional expansion capabilities for future service satellites. A set of 420 codes was selected from a Weil-based code derived from the prime number 10247, which is larger than the 10243 prime number used to derive BeiDou’s B1C Weil sequences. Both the initial set of 210 codes and the expanded set of 420 codes are shown to provide the best cross-correlation of any 10230-chip satellite navigation codes. The performance is demonstrated for hierarchical sets of spreading codes optimized and organized in sets of 30 codes. The work also compares LunaNet’s AFS to terrestrial GNSS signals in terms of acquisition, tracking, and data demodulation performance. Performance is evaluated for receivers that only track the 1.023 MCPS data channel spreading code for low SWaP IoT use cases, as well as for receivers that track both the 1.023 MCPS data channel and the 5.115 MCPS pilot channel spreading code for high-performance use cases. Performance is assessed in the presence of interference and thermal noise. The analysis is performed in terms of expected operating conditions on the lunar surface. Several unique flexibility aspects of the augmented forward signal are described, including the use of the Q channel’s secondary and tertiary codes to enable variable coherent integrations during acquisition. This is compared to GNSS signals such as L5/E5 and MBOC in terms of achievable processing gain for interference mitigation versus acquisition complexity. The work details acquisition and tracking techniques used to optimally acquire and track the primary, secondary, and tertiary codes on the Q channel, as well as acquisition of the I channel spreading code. Acquisition of the 8 ms, Q channel spreading code is also compared to joint acquisition of the I and Q channel primary codes in noise and interference environments

LCRNS↗

NASA NTRS2002

Commercial-Off-The-Shelf Microelectromechanical Systems (MEMS) Flow-Measurement Probes Fabricated And Assembled

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at the NASA Glenn Research Center have been fabricating packaging components and assembling a set of unique probes using commercial-off-the-shelf microelectromechanical systems (MEMS) integrated circuits (computer chips). Using MEMS as an alternative has some compelling advantages over standard measurement devices. Sensor technologies have matured through high-production usage in industries such as automotive and aircraft manufacturers. Currently, MEMS are the choice in applications such as tire pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Conventional instrumentation uses tubing buried in the model aerodynamic surfaces or wind tunnel walls. The measurements are made when pressure is introduced at the tube opening. The pressure then must travel the tubing for lengths ranging from 20 to hundreds of feet before reaching an electronic signal conditioner. This condition causes a considerable amount of damping and requires measurements to be made only after the test rig has reached steady-state operation. The electronic MEMS pressure sensor is able to take readings continuously under dynamic states in nearly real time. The use of stainless steel tubing for pressure measurements requires many tubes to be cleaned, cut to length, carefully installed, and delicately deburred and spliced for use. A cluster of a few hundred 1/16-in.- (0.0625-in.-) diameter tubes (not uncommon in research testing facilities) can be several inches in diameter and may weigh enough to require two men to handle. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of the 1/16-in. tubing with room to spare. The P592 piezoresistive silicon pressure sensor (Lucas NovaSensor, Fremont, CA) was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The chip is 1 mm square by 0.6 mm thick (0.039 by 0.023 in.) with 0.12-mm (0.005-in.) wire connection tabs. Three MEMS chips were used to build the first type of flow-angularity probe. This MEMS probe will be demonstrated as an alternative to a standard tube type "Cobra Probe" now used routinely in wind tunnel and aeronautical hardware applications. The response time and accuracy would allow the probe to be translated on an actuator across a flow field, yielding precision dynamic measurements not possible with conventional instrumentation. The low profile, the minimal power requirement, the rugged construction, and the moderate cost all contribute to making MEMS sensors the enticing choice instrument in future research measurement needs. The MEMS probe efforts are a continuation of work initiated by Brian Willis, without whose foresight and efforts this project would never have been realized. This task was funded through cooperation with the NASA Electronic Parts and Packaging (NEPP) program at the Jet Propulsion Laboratory.

Redding, Chip↗

NASA NTRS2004

COTS MEMS Flow-Measurement Probes

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at Glenn Research Center have been fabricating packaging components and assembling a set of unique probes that contain commercial off-the-shelf (COTS) microelectromechanical systems (MEMS) sensor chips. MEMS sensor chips offer some compelling advantages over standard macroscopic measurement devices. MEMS sensor technology has matured through mass production and use in the automotive and aircraft industries. At present, MEMS are the devices of choice for sensors in such applications as tire-pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Compactness, minimality of power demand, rugged construction, and moderate cost all contribute to making MEMS sensors attractive for instrumentation for future research. Conventional macroscopic flow-measurement instrumentation includes tubes buried beneath the aerodynamic surfaces of wind-tunnel models or in wind-tunnel walls. Pressure is introduced at the opening of each such tube. The pressure must then travel along the tube before reaching a transducer that generates an electronic signal. The lengths of such tubes typically range from 20 ft (approx.= 6 m) to hundreds of feet (of the order of 100 m). The propagation of pressure signals in the tubes damps the signals considerably and makes it necessary to delay measurements until after test rigs have reached steady-state operation. In contrast, a MEMS pressure sensor that generates electronic output can take readings continuously under dynamic conditions in nearly real time. In order to use stainless-steel tubing for pressure measurements, it is necessary to clean many tubes, cut them to length, carefully install them, delicately deburr them, and splice them. A cluster of a few hundred 1/16-in.- (approx.=1.6-mm-) diameter tubes (such clusters are common in research testing facilities) can be several inches (of the order of 10 cm) in diameter and could weigh enough that two technicians are needed to handle it. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of a 1/16-in. tube with room to spare. The Lucas NovaSensor P592 piezoresistive silicon pressure sensor was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The sensor chip is 1 mm square by 0.6 mm thick (about 0.039 by 0.039 by 0.024 in.) and includes 0.12-mm (approx.=0.005-in.) wire connection tabs. The figure shows a flow-angularity probe that was built by use of three such MEMS chips. It is planned to demonstrate this MEMS probe as an alternative to a standard tube-type "Cobra" probe now used routinely in wind tunnels and aeronautical hardware. This MEMS probe could be translated across a flow field by use of a suitable actuator, so that its accuracy and the shortness of its response time could be exploited to obtain precise dynamic measurements of a sort that cannot be made by use of conventional tubing-based instrumentation.

Redding, Chip↗

NASA NTRS2003

High-Performance Solid-State W-Band Power Amplifiers

The figure shows one of four solid-state power amplifiers, each capable of generating an output power greater than or equal to 240 mW over one of four overlapping frequency bands from 71 to 106 GHz. (The bands are 71 to 84, 80 to 92, 88 to 99, and 89 to 106 GHz.) The amplifiers are designed for optimum performance at a temperature of 130 K. These amplifiers were developed specifically for incorporation into frequency-multiplier chains in local oscillators in a low-noise, far-infrared receiving instrument to be launched into outer space to make astrophysical observations. The designs of these amplifiers may also be of interest to designers and manufacturers of terrestrial W-band communication and radar systems. Each amplifier includes a set of six high-electron-mobility transistor (HEMT) GaAs monolithic microwave integrated-circuit (MMIC) chips, microstrip cavities, and other components packaged in a housing made from A-40 silicon-aluminum alloy. This alloy was chosen because, for the original intended spacecraft application, it offers an acceptable compromise among the partially competing requirements for high thermal conductivity, low mass, and low thermal expansion. Problems that were solved in designing the amplifiers included designing connectors and packages to fit the available space; designing microstrip signal-power splitters and combiners; matching of impedances across the frequency bands; matching of the electrical characteristics of those chips installed in parallel power-combining arms; control and levelling of output power across the bands; and designing the MMICs, microstrips, and microstrip cavities to suppress tendencies toward oscillation in several modes, both inside and outside the desired frequency bands.

Gaier, Todd↗

NASA NTRSDate not supplied

Open-source Wireless Sensor Network (Wi-Se Net) for Flexible Deployment

Wireless sensors, especially if battery powered, have a number of advantages over wired sensors for flexible or temporary diagnostic deployment in a field or lab setting. Recent advances in wireless technology and microprocessor boards have produced a variety of inexpensive off-the shelf chips which can communicate wirelessly with simple protocols. This paper describes the design and implementation of a highly customizable wireless sensor network (called WiSe Net) using inexpensive open-source hardware components as wireless nodes. These wireless sensor nodes can transmit data at a rate <250 Hz, can be battery powered, and have a small footprint (2x5 cm). In addition, a preliminary over-the-air programming system was developed to allow for simple wireless configuration when active. The network performance was demonstrated by taking distributed and electrically isolated temperature measurements on a high-voltage lab apparatus. Although this test case is in a laboratory setting, this network architecture could be easily repurposed for various other forms of monitoring

Wireless Sensor Network↗

NASA NTRSDate not supplied

Open-source Wireless Sensor Network (Wi-Se Net) for Flexible Deployment

Wireless Sensor Network↗

NASA NTRSDate not supplied

Open-source Wireless Sensor Network (Wi-Se Net) for Flexible Deployment

Wireless sensors, especially if battery powered, have a number of advantages over wired sensors for flexible or temporary diagnostic deployment in a field or lab setting. Recent advances in wireless technology and microprocessor boards have produced a variety of inexpensive off-the shelf chips which can communicate wirelessly with simple protocols. This paper describes the design and implementation of a highly customizable wireless sensor network (called Wi-Se Net) using inexpensive open-source hardware components as wireless nodes. These wireless sensor nodes can transmit data at a rate <250 Hz, can be battery powered, and have a small footprint (2x5 cm). In addition, a preliminary over-the-air programming system was developed to allow for simple wireless configuration when active. The network performance was demonstrated by taking distributed and electrically isolated temperature measurements on a high-voltage lab apparatus. Although this test case is in a laboratory setting, this network architecture could be easily repurposed for various other forms of monitoring.

Wireless Sensor Network↗

NASA NTRS2003

Integrated Electrode Arrays for Neuro-Prosthetic Implants

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Brandon, Erik↗

NASA NTRS1991

Report on the formal specification and partial verification of the VIPER microprocessor

The VIPER microprocessor chip is partitioned into four levels of abstractions. At the highest level, VIPER is described with decreasingly abstract sets of functions in LCF-LSM. At the lowest level are the gate-level models in proprietary CAD languages. The block-level and gate-level specifications are also given in the ELLA simulation language. Among VIPER's deficiencies are the fact that there is no notion of external events in the top-level specification, and it is impossible to use the top-level specifications to prove abstract properties of programs running on VIPER computers. There is no complete proof that the gate-level specifications implement the top-level specifications. Cohn's proof that the major-state machine correctly implements the top-level specifications has no formal connection with any of the other proof attempts. None of the latter address resetting the machine, memory timeout, forced error, or single step modes.

Brock, Bishop↗