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In this paper, analytical bounds on the performance of parallel concatenation of two codes, known as turbo codes, and serial concatenation of two codes over fading channels are obtained.
A bit synchronizer for a split phase PCM transmission is reported that includes three loop circuits which receive incoming phase coded PCM signals. In the first loop, called a Q-loop, a generated, phase coded, PCM signal is multiplied with the incoming signals, and the frequency and phase of the generated signal are nulled to that of the incoming subcarrier signal. In the second loop, called a B-loop, a circuit multiplies a generated signal with incoming signals to null the phase of the generated signal in a bit phase locked relationship to the incoming signal. In a third loop, called the I-loop, a phase coded PCM signal is multiplied with the incoming signals for decoding the bit information from the PCM signal. A counter means is used for timing of the generated signals and timing of sample intervals for each bit period.
This paper reports the simulated performance of each of the nine accumulate-repeat-4-jagged-accumulate (AR4JA) low-density parity-check (LDPC) codes [3] when used in conjunction with binary phase-shift-keying (BPSK), quadrature PSK (QPSK), 8-PSK, 16-ary amplitude PSK (16- APSK), and 32-APSK.We also report the performance under various mappings of bits to modulation symbols, 16-APSK and 32-APSK ring scalings, log-likelihood ratio (LLR) approximations, and decoder variations. One of the simple and well-performing LLR approximations can be expressed in a general equation that applies to all of the modulation types.
Motivated by previous work of Li and Rimoldi for obtaining bandwidth efficient TCM signals with finite decoding delay, we present an alternative representation for their encoder/signal mapper transmitter structure which merely consists of a single filter having an input equal to the equivalent of the inoput data bits in their implementation.
Small, programmable, high speed PCM subsystem, supports the variety of signals inherent in sophisticated equipment. A signal generated by a transducer is first conditioned to the proper signal range, then sampled by an external multiplexer or by the subsystem directly and then converted and transmitted to a receiving station.
Time-shared integrate-hold-dump circuits separate the dc level due to the signal /bit information/ from the dc signal due to the baseline error. The system detects the baseline error, filters it, and then algebraically adds enough voltage to a servo loop to reduce the error to zero.
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System for recording and reproducing PCM data from data stored on magnetic tape
Signal is demodulated and synchronized by three loop circuits: ''Q'' loop uses quadrature signal to stabilize frequency; ''B'' loop acts on baseboard signal to stabilize phase; and decoding ''I'' loop acts on in-phase signal. Synchronizer may be used to eliminate false-lock.
A PCM storage device/data analyzer is described. This instrument is a peripheral plug-in board especially built to enable a personal computer to store and analyze data from a PCM source. This board and custom written software turns a computer into a snapshot PCM decommutator. This instrument will take in and store many hundreds or thousands of PCM telemetry data frames, then sift through them over and over again. The data can be converted to any number base and displayed, examined for any bit dropouts or changes in particular words or frames, graphically plotted, or statistically analyzed. This device was designed and built for use on the NASA Sounding Rocket Program for PCM encoder configuration and testing.
Some new codes are presented which have good performance on Rician fading channel with small decoding complexities. A new M-way partition chain is proposed for the L x MPSK (L less than or equal to M) signal set which maximizes the intra-set distance of each subset at each partition level. Based on this partition chain, a class of asymptotical optimum codes was found. For M = 4, these codes have both large symbol distances and product distances. Multi-level coding scheme allows to construct a code by hand such that the code meets some desired parameters, e.g., symbol distance, product distance, etc. In design of a multi-level code, all factors were considered which affect the performance and complexity of the code, such as, the decoding scheme, decoding complexity, and performance under the decoding scheme, e.g., if the multi-stage decoding scheme is used, the performance degradation due to the suboptimum decoding is taken into consideration. The performance for most of the presented codes was simulated on Rayleigh fading channel, and the results show that these codes have good performance with small decoding complexities.
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This paper presents the communications challenges for the MER mission, the use of DSN and MER tools to maximize the science return, and the application of standards-based relays to the problem. To date, more than 90% of the data returned from MER has been returned via relays, not direct-to-Earath (DTE).
Methods and apparatus are provided for telemetry processing using a telemetry processor. The telemetry processor can include a plurality of communications interfaces, a computer processor, and data storage. The telemetry processor can buffer sensor data by: receiving a frame of sensor data using a first communications interface and clock data using a second communications interface, receiving an end of frame signal using a third communications interface, and storing the received frame of sensor data in the data storage. After buffering the sensor data, the telemetry processor can generate an encapsulated data packet including a single encapsulated data packet header, the buffered sensor data, and identifiers identifying telemetry devices that provided the sensor data. A format of the encapsulated data packet can comply with a Consultative Committee for Space Data Systems (CCSDS) standard. The telemetry processor can send the encapsulated data packet using a fourth and a fifth communications interfaces.
The commercial impact and technical success of Trellis Coded Modulation seems to illustrate that, if Shannon's capacity is going to be neared, the modulation and coding of an analogue signal ought to be viewed as an integrated process. More recent work has focused on going beyond the gains obtained for Average White Gaussian Noise and has tried to combine the coding/modulation with adaptive equalization. The motive is to gain similar advances on less perfect or idealized channels.
An architecture and a hardware prototype of a flexible trellis modem/codec (FTMC) transmitter are presented. The theory of operation is built upon a pragmatic approach to trellis-coded modulation that emphasizes power and spectral efficiency. The system incorporates programmable modulation formats, variations of trellis-coding, digital baseband pulse-shaping, and digital channel precompensation. The modulation formats examined include (uncoded and coded) binary phase shift keying (BPSK), quatenary phase shift keying (QPSK), octal phase shift keying (8PSK), 16-ary quadrature amplitude modulation (16-QAM), and quadrature quadrature phase shift keying (Q squared PSK) at programmable rates up to 20 megabits per second (Mbps). The FTMC is part of the developing test bed to quantify modulation and coding concepts.