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DOE OSTI2025

Low-overhead transversal fault tolerance for universal quantum computation

Fast, reliable logical operations are essential for realizing useful quantum computers. By redundantly encoding logical qubits into many physical qubits and using syndrome measurements to detect and correct errors, we can achieve low logical error rates. However, for many practical quantum error correction codes such as the surface code, owing to syndrome measurement errors, standard constructions require multiple extraction rounds—of the order of the code distance d—for fault-tolerant computation, particularly considering fault-tolerant state preparation. Here we show that logical operations can be performed fault-tolerantly with only a constant number of extraction rounds for a broad class of quantum error correction codes, including the surface code with magic state inputs and feedforward, to achieve ‘transversal algorithmic fault tolerance’. Through the combination of transversal operations7 and new strategies for correlated decoding, despite only having access to partial syndrome information, we prove that the deviation from the ideal logical measurement distribution can be made exponentially small in the distance, even if the instantaneous quantum state cannot be made close to a logical codeword because of measurement errors. We supplement this proof with circuit-level simulations in a range of relevant settings, demonstrating the fault tolerance and competitive performance of our approach. Furthermore, our work sheds new light on the theory of quantum fault tolerance and has the potential to reduce the space–time cost of practical fault-tolerant quantum computation by over an order of magnitude.

Zhou, Hengyun [QuEra Computing, Boston, MA (United↗

DOE OSTI2025

Fault-tolerant operation and materials science with neutral atom logical qubits

We report on the fault-tolerant operation of logical qubits on a neutral atom quantum computer, with logical performance surpassing physical performance for multiple circuits including Bell state preparation (12x error reduction), random circuits (15x), and a prototype Anderson Impurity Model ground state solver for materials science applications (up to 6x, non-fault-tolerantly). The logical qubits are implemented via the [[4, 2, 2]] code (C 4 ). Our work constitutes the first complete realization of the benchmarking protocol proposed by Gottesman 2016 demonstrating results consistent with fault tolerance. In light of recent advances on applying concatenated C 4 /C 6 detection codes to achieve error correction with high code rates and thresholds, our work can be regarded as a building block towards a practical scheme for fault tolerant quantum computation. Our demonstration of a materials science application with logical qubits particularly demonstrates the immediate value of these techniques on current experiments.

36 MATERIALS SCIENCE↗

DOE OSTI2022

Distributed Quantum Error Correction for Chip-Level Catastrophic Errors

Quantum error correction holds the key to scaling up quantum computers. Cosmic ray events severely impact the operation of a quantum computer by causing chip-level catastrophic errors, essentially erasing the information encoded in a chip. Here, in this work, we present a distributed error correction scheme to combat the devastating effect of such events by introducing an additional layer of quantum erasure error correcting code across separate chips. We show that our scheme is fault tolerant against chip-level catastrophic errors and discuss its experimental implementation using superconducting qubits with microwave links. Our analysis shows that in state-of-the-art experiments, it is possible to suppress the rate of these errors from 1 per 10 s to less than 1 per month.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

Deep reinforcement learning for class imbalance fault diagnosis of equipment in nuclear power plants

In equipment fault diagnosis in nuclear power plants, there may be far more samples in one class (e.g., a health state) than in another class (e.g., a fault state). The distribution of data in each class is highly skewed. Most machine learning algorithms are suitable for balanced training datasets. When faced with imbalanced samples, these algorithms tend to provide good identification for the majority classes and bias for the minority classes. However, the misclassification of minority classes can lead to high costs. To address the above problem, this paper develops a deep reinforcement learning-based diagnosis method that models fault diagnosis as a sequential decision-making process. At each time step, the agent receives the state of the environment represented by the training samples and then takes a diagnosis action guided by a policy. If the action is correct/incorrect, the agent receives a positive/negative reward. The reward for minority classes is higher than that for majority classes. The agent’s goal is to obtain as many cumulative rewards as possible in the process, i.e., to identify the sample as correctly as possible. Six demonstration scenarios are constructed, depending on the selected fault datasets and the designed model structures. Experiments show that the proposed method achieves a higher weighted-averaged F1 score than the classical supervised learning method in most cases of class imbalance. Finally, the proposed method has potential applications in the field of class imbalance fault diagnosis of equipment in nuclear power plants.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

DOE OSTI2022

Resilience Design Patterns: A Structured Approach to Resilience at Extreme Scale (V.2.0)

Reliability is a serious concern for future extreme-scale high-performance computing (HPC) systems. Projections based on the current generation of HPC systems and technology roadmaps suggest the prevalence of very high fault rates in future systems. The errors resulting from these faults will propagate and generate various kinds of failures, which may result in outcomes ranging from result corruptions to catastrophic application crashes. Therefore, the resilience challenge for extreme-scale HPC systems requires coordination between various hardware and software technologies that are capable of handling a broad set of fault models at accelerated fault rates. Also, due to practical limits on power consumption in future HPC systems, they are likely to embrace innovative architectures, increasing the levels of hardware and software complexities. Therefore, the techniques that seek to improve resilience must navigate the complex trade-off space between resilience and the overheads to power consumption and performance. While the HPC community has developed various resilience solutions, application-level techniques as well as system-based solutions, the solution space of HPC resilience techniques remains fragmented. There are no formal methods to integrate the various HPC resilience techniques into composite solutions, nor are there methods to holistically evaluate the adequacy and efficacy of such solutions in terms of their protection coverage, and their performance & power efficiency characteristics. Additionally, few implementations of current resilience solutions are portable to newer architectures and software environments that will be deployed on future systems. We developed a new structured approach to the management of HPC resilience using the concept of resilience-based design patterns. In general, a design pattern is a repeatable solution to a commonly occurring problem. We identified the well-known solutions that are commonly used to deal with faults, errors and failures in HPC systems. In the initial design patterns specification (version 1.0), we described the various solutions, which address specific problems in the design of resilient HPC environments, in the form of patterns. Each pattern describes a problem caused by a fault, error or failure event in an HPC environment, and then describes the core of the solution of the problem in such a way that this solution may be adapted to different systems and implemented at different layers of the system stack. The catalog of these resilience design patterns provides designers with a collection of design elements. To construct complete resilience solutions using combinations of various patterns, we defined a framework that enhances HPC designers' understanding of the important constraints and the opportunities for the design patterns to be implemented and deployed at various layers of the system stack. The design framework is also useful for establishing interfaces and mechanisms to coordinate flexible fault management across hardware and software components, as well as to consider the trade-off between performance, resilience, and power consumption when constructing a solution. The resilience design patterns specification version 1.1 included more detailed explanations of the pattern solutions, the context in which the patterns are applicable, and the implications for hardware or software design. It also provided several additional examples and detailed case studies to demonstrate the use of patterns to build realistic solutions. In version 1.2 of the specification document, we have improved the pattern descriptions, including graphical representations of the pattern components. These improvements are largely based on critical comments, feedback and suggestions received from pattern experts and readers of the previous versions of the specification. The pattern classification has been modified to further clarify the relationships between pattern categories. This version of the specification also introduces a pattern language for resilience design patterns. The pattern language presents the patterns in the catalog as a network, revealing the relations among the resilience patterns. The language provides designers with the means to explore alternative techniques for handling a specific fault model that may have different efficiency and complexity characteristics. Using the pattern language also enables the design and implementation of comprehensive resilience solutions as a set of interconnected resilience patterns that can be instantiated across layers of the system stack. The overall goal of this work is to provide hardware and software designers, as well as the users and operators of HPC systems, a systematic methodology for the design and evaluation of resilience technologies in HPC systems that keep scientific applications running to a correct solution in a timely and cost-efficient manner despite frequent faults, errors, and failures of various types. Version 2.0 expands the resilience design pattern classification and catalog to include self-stabilization patterns and reliability, availability and performance models for each structural pattern.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

On the Language of Reliability: A System Engineer Perspective

In its classical definition, risk is defined by three elements: what can go wrong, what are its consequences, and how likely is it to occur? While this definition makes sense in a regulatory-based framework where for the current fleet of operating light water reactors (LWRs), the risks associated with nuclear power plants typically are characterized in terms of core damage and large early release frequency (LERF), this approach does not provide a useful snapshot of the health of the plant from a broader perspective. This is due to the very narrow context in which the term “risk” typically is defined as nuclear safety aspects that have the potential to impact public health. In this paper, we take the viewpoint of nuclear safety that is reflective of the current fleet of operating LWRs for which core damage frequency and LERF are appropriate metrics. For other advanced reactor designs, other more applicable technology neutral metrics of reactor safety metrics would be specified. A possible alternate path would start by redefining the word risk with a broader meaning that better reflects the needs of a system health and asset management decision-making process. Rather than asking how likely an event could occur (in probabilistic terms), we can ask how far this event is from occurring. Our approach starts by defining and quantifying component and system health in terms of a “distance” between its actual and limiting conditions, i.e., determination of the margin that exists between the current state/condition and the state where the component/system is no longer capable of achieving its intended function. A margin is a measure that is more reflective of the current state or performance of a component, and therefore more closely tied to decisions that are made on an ongoing basis. Further, we will show how, given the data available from plant equipment reliability and monitoring (e.g., pump vibration data) and prognostic (e.g., component remaining useful life estimation) data, a margin can be described and determined for all types of maintenance approaches (e.g., corrective or predictive maintenance). We show how classical reliability models (e.g., fault trees) can be used to quantify the system margin provided component margin values. In the approach described in this paper, the propagation of margin values through classical reliability models are not performed using classical probabilistic calculations applied to sets (as performed in a typical plant probabilistic risk assessment). Instead, we show how it is possible to propagate margin values through Boolean logic gates (i.e., AND and OR operators) through distance-based operations.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

Understanding Mixed Precision GEMM with MPGemmFI: Insights into Fault Resilience

Emerging deep learning workloads urgently need fast general matrix multiplication (GEMM). Thus, one of the critical features of machine-learning-specific accelerators such as NVIDIA Tensor Cores, AMD Matrix Cores, and Google TPUs is the support of mixed-precision enabled GEMM. For DNN models, lower-precision FP data formats and computation offer acceptable correctness but significant performance, area, and memory footprint improvement. While promising, the mixed-precision computation on error resilience remains unexplored. To this end, we develop a fault injection framework that systematically injects fault into the mixed-precision computation results. We investigate how the faults affect the accuracy of machine learning applications. Based on the characteristics of error resilience, we offer lightweight error detection and correction solutions that significantly improve the overall model accuracy by 75% if the models experience hardware faults. The solutions can be efficiently integrated into the accelerator's pipelines.

Fang, Bo↗

DOE OSTI2023

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.

cryogenic optimization↗

DOE OSTI2024

Flag Gadgets Based on Classical Codes

Fault-tolerant syndrome extraction is a key ingredient in implementing fault-tolerant quantum computation. While conventional methods use a number of extra qubits that are linear in the weight of the syndrome, several improvements have been introduced using flag gadgets. In this work, we develop a framework to design flag gadgets using classical codes. Using this framework, we show how to perform fault-tolerant syndrome extraction for any stabilizer code with arbitrary distance using exponentially fewer qubits than conventional methods when qubit measurement and reset are relatively slow compared to a round of error correction. In particular, our method requires only ( 2 t + 1 ) t ⌈ log 2 ( w ) ⌉ flag qubits to fault-tolerantly measure a weight- w stabilizer. We further take advantage of the saving provided by our construction to fault-tolerantly measure multiple stabilizers using a single gadget and show that it maintains the same exponential advantage when it is used to fault-tolerantly extract the syndromes of quantum low-density parity-check codes. Using the developed framework, we perform computer-assisted search to find several small examples where our constructions reduce the number of qubits required. These small examples may be relevant to near-term experiments on small-scale quantum computers. Published by the American Physical Society 2024

Anker, Benjamin↗

DOE OSTI2026

Concatenated dual displacement code for continuous-variable quantum error correction

The continuous-variable (CV) Gaussian no-go theorem fundamentally limits the suppression of Gaussian displacement errors using only Gaussian gates and states. Prior studies have employed Gottesman-Kitaev-Preskill (GKP) states as ancillary qumodes to suppress small Gaussian displacement errors. However, when the displacement magnitude becomes large, inevitable lattice-crossing errors arise beyond the correctable range of the GKP state. To address this issue, we concatenate the Gaussian-noise-suppression circuit with an outer analog Steane code that corrects such occasional lattice-crossing events as well as other abrupt displacement errors. Contrary to conventional concatenation, which primarily aims to reduce logical error rates, the Steane-GKP duality in encoding provides complementary protection against displacement errors at different scales: The inner GKP layer employs non-Gaussian resources to suppress continuous Gaussian noise and reduce residual variance, while the outer analog Steane code corrects discrete lattice-crossing events that exceed the GKP correctable range. It is precisely this separation of error-mitigation roles that enables CV error correction. In contrast to prior work on concatenating GKP and repetition codes to establish error correction for discrete qubit/qudit encoding, we provide correction in the continuous encoding space. Analytical studies show that, under infinite squeezing, the concatenated code suppresses the variance of Gaussian displacement errors acting on all qumodes by up to 50%, while enabling unbiased correction of lattice-crossing errors with a success probability determined by the ratio between the residual Gaussian error standard deviation and the lattice-crossing magnitude. Even with finite squeezing, the proposed architecture still provides Gaussian-error suppression and lattice-crossing correction. Moreover, the presence of the outer analog Steane code relaxes the squeezing requirement of the inner GKP states, indicating near-term experimental feasibility. This work establishes a viable route toward fault-tolerant continuous-variable quantum computation and provides insight into the design of concatenated CV error-correcting architectures.

quantum error correction↗

DOE OSTI2021

Nuclear Power Fault Diagnostics and Preventative Maintenance Optimization

Operation and maintenance costs for nuclear power plants are very large. Reactors are starting to shut down even after their operating licenses have been extended, because they are not price competitive compared to other energy sources. The nuclear industry is witnessing early closure of nuclear power plants due to economic reasons despite excellent safety records. Therefore, it is imperative to reduce costs to prevent these early closures. This paper showcases recent research into advanced fault diagnostics techniques and preventative maintenance optimization to reduce these maintenance costs. This report focuses on the condensate and feedwater system for both pressurized and boiling water reactor systems. The computerized maintenance management system, which contains the plant’s digital record of all the corrective- and preventative-maintenance work orders, was used as a ground truth to locate potential faults and label the process data as healthy or faulty. Various feature extraction techniques were utilized to further differentiate the faults from the healthy data. Support vectors machines were used to categorize other test sets of process data as healthy or faulty through a cross validation procedure. Similar faults were not found within this system leading to preventative maintenance optimization. Unnecessary amounts of preventative maintenance lead to inflated maintenance costs. This paper summarizes the steps for preventative maintenance optimization from component health determination to recommendation for action. This optimization was completed for condensate pumps, condensate booster pumps, and the respective motors that drive them.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

DOE OSTI2021

Nuclear Power Fault Diagnostics and Preventative Maintenance Optimization

The nuclear industry is beginning to see reactors shut down—even after their operating licenses have been extended—because they are not economically competitive with other energy sources. These early closures happen primarily due to economic reasons, despite excellent safety records. Therefore, it is imperative to reduce costs in order to prevent these early closures. One of the contributors to these economic reasons is the large operations and maintenance costs. This paper showcases recent research on advanced fault diagnostics techniques and preventative maintenance optimization (PMO) for reducing NPP maintenance costs. Specifically, it focuses on the feedwater and condensate system (FWCS) for both pressurized- and boiling-water reactor (BWR) systems. The computerized maintenance management system (CMMS), which contains the plant’s digital record of all corrective maintenance (CM) and preventative maintenance (PM) work orders, provided the ground truth for locating potential faults and labeling the process data as either healthy or faulted. Various feature extraction techniques were used to further differentiate the faulted data from the healthy data. Through a cross-validation procedure, support vectors machines were used to label other test sets of process data as either healthy or faulted. With relatively few faults identified in the BWR system, the potential for PMO opens up, since an unnecessary amount of PM leads to inflated maintenance costs. The steps for PMO are summarized, from component health determinations to recommendations for action. An example of PMO assessment is presented for condensate pumps, condensate booster pumps, and the respective motors that drive them.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

Nuclear Power Fault Diagnostics and Preventative Maintenance Optimization NPIC presentation

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2025

Atomic-Scale Behavior of Radiation-Resistant ZnO under High-Energy Electron Bombardment

Understanding the atomic structure and defect characteristics of ZnO thin films is crucial for optimizing their electronic properties and performance in advanced applications. Here, we investigate the atomic structure and defect characteristics of atomic layer deposition (ALD)-grown ZnO thin films by using aberration-corrected scanning transmission electron microscopy (STEM). Atomic-resolution imaging identifies prevalent stacking faults, dipole disorder, and various grain boundary types, which are believed to influence the electronic properties of ZnO. Additionally, real-time electron beam exposure experiments demonstrate structural transformations, including crystal growth and surface rearrangements. These findings provide insights into the growth mechanisms of ALD ZnO under high-energy electron irradiation conditions, an important finding for the use of polycrystalline ZnO wide bandgap semiconductors in space-like conditions. In conclusion, our results underscore the capability of STEM in directly visualizing and quantifying atomic-scale defects and beam-induced transformations in radiation-resistant ZnO.

Defects↗

DOE OSTI2022

Masked fault detection for reliable low voltage cache operation

Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

Ganapathy, Shrikanth↗

DOE OSTI2024

Phase diagram of the three-dimensional subsystem toric code

Subsystem quantum error-correcting codes typically involve measuring a sequence of noncommuting parity check operators. They can sometimes exhibit greater fault tolerance than conventional codes, which use commuting checks. However, unlike subspace codes, it is unclear if subsystem codes—in particular their advantages—can be understood in terms of ground-state properties of a physical Hamiltonian. In this paper, we address this question for the three-dimensional subsystem toric code (3D STC), as recently constructed by Kubica and Vasmer [], which exhibits single-shot error correction. Motivated by a conjectured relation between single-shot properties and thermal stability, we study the zero- and finite-temperature phases of an associated noncommuting Hamiltonian. By mapping the Hamiltonian model to a pair of 3D Z 2 gauge theories coupled by a kinetic constraint, we find various phases at zero temperature, all separated by first-order transitions: There are 3D toric code-like phases with deconfined point-like excitations in the bulk, and there are phases with a confined bulk supporting a 2D toric code on the surface when appropriate boundary conditions are chosen. The latter is similar to the surface topological order present in 3D STC. However, the similarities between the single-shot correction in 3D STC and the confined phases are only partial: they share the same sets of degrees of freedom, but they are governed by different dynamical rules. Instead, we argue that the process of single-shot error correction can more suitably be associated with a path (rather than a point) in the zero-temperature phase diagram, a perspective, which inspires alternative measurement sequences enabling single-shot error correction. Moreover, since none of the above-mentioned phases survives at nonzero temperature, the single-shot error-correction property of the code does not imply thermal stability of the associated Hamiltonian phase. Published by the American Physical Society 2024

Li, Yaodong (ORCID:0000000337421944)↗

DOE OSTI2025

Toward a 2D Local Implementation of Quantum Low-Density Parity-Check Codes

Geometric locality is an important theoretical and practical factor for quantum low-density parity-check (qLDPC) codes that affects code performance and ease of physical realization. For device architectures restricted to two-dimensional (2D) local gates, naively implementing the high-rate codes suitable for low-overhead fault-tolerant quantum computing incurs prohibitive overhead. In this work, we present an error-correction protocol built on a bilayer architecture that aims to reduce operational overheads when restricted to 2D local gates by measuring some generators less frequently than others. We investigate the family of bivariate-bicycle qLDPC codes and show that they are well suited for a parallel syndrome-measurement scheme using fast routing with local operations and classical communication (LOCC). Through circuit-level simulations, we find that in some parameter regimes, bivariate-bicycle codes implemented with this protocol have logical error rates comparable to the surface code while using fewer physical qubits. Published by the American Physical Society 2025

Berthusen, Noah (ORCID:0000000275862786)↗

DOE OSTI2024

Quantum error thresholds for gauge-redundant digitizations of lattice field theories

In the quantum simulation of lattice gauge theories, gauge symmetry can be either fixed or encoded as a redundancy of the Hilbert space. While gauge-fixing reduces the number of qubits, keeping the gauge redundancy can provide code space to mitigate and correct quantum errors by checking and restoring Gauss’s law. In this work, we consider the correctable errors for generic finite gauge groups and design the quantum circuits to detect and correct them. We calculate the error thresholds below which the gauge-redundant digitization with Gauss’s law error correction has better fidelity than the gauge-fixed digitization involving only gauge-invariant states. Our results provide guidance for fault-tolerant quantum simulations of lattice gauge theories. Published by the American Physical Society 2024

97 MATHEMATICS AND COMPUTING↗