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DOE OSTI2024

Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamak

Active feedback control in magnetic confinement fusion devices is desirable to mitigate plasma instabilities and enable robust operation. Optical high-speed cameras provide a powerful, non-invasive diagnostic and can be suitable for these applications. Here, in this study, we process high-speed camera data, at rates exceeding 100 kfps, on in situ field-programmable gate array (FPGA) hardware to track magnetohydrodynamic (MHD) mode evolution and generate control signals in real time. Our system utilizes a convolutional neural network (CNN) model, which predicts the n = 1 MHD mode amplitude and phase using camera images with better accuracy than other tested non-deep-learning-based methods. By implementing this model directly within the standard FPGA readout hardware of the high-speed camera diagnostic, our mode tracking system achieves a total trigger-to-output latency of 17.6 μs and a throughput of up to 120 kfps. This study at the High Beta Tokamak-Extended Pulse (HBT-EP) experiment demonstrates an FPGA-based high-speed camera data acquisition and processing system, enabling application in real-time machine-learning-based tokamak diagnostic and control as well as potential applications in other scientific domains.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2014

A high-speed, high-efficiency phase controller for coherent beam combining based on SPGD algorithm

A phase controller for coherent beam combining (CBC) of fibre lasers has been designed and manufactured based on a stochastic parallel gradient descent (SPGD) algorithm and a field programmable gate array (FPGA). The theoretical analysis shows that the iteration rate is higher than 1.9 MHz, and the average compensation bandwidth of CBC for 5 or 20 channels is 50 kHz or 12.5 kHz, respectively. The tests show that the phase controller ensures reliable phase locking of lasers: When the phases of five lasers are locked by the improved control strategy with a variable gain, the energy encircled in the target is increased by 23 times than that in the single output, the phase control accuracy is better than λ/20, and the combining efficiency is 92%. (control of laser radiation parameters)

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2020

Preliminary design overview and performance assessment of the ITER low-field side reflectometer

The design of the ITER low-field side reflectometer (LFSR) has matured to a complete end-to-end preliminary design. LFSR will supply three key plasma measurements: (1) electron density profile, (2) electron density fluctuations, and (3) poloidal rotation. Simultaneous measurements of the three quantities are enabled by an array of six monostatic antennas which inject from an equatorial port on the outboard side of the ITER vessel. Low-loss transmission lines, consisting of corrugated, overmoded waveguide and miter bends, transmit the 30–165 GHz, O- and X-mode signals to and from the ITER plasma. Integrated transmission-line components serve a range of purposes, such as protection from high-power stray radiofrequency radiation, accommodation of transmission-line displacement, and simultaneous measurement of reference and plasma phases during the discharge. Broadband transmission signals are realized by full-band microwave transceivers combined with quasi-optical multiplexing. A field-programmable gate array (FPGA) processor demodulates the profile reflectometer signals, enabling real-time density profile measurements for plasma control system feedback. A full-scale transmission line test facility provides an integrated environment to assess the performance of critical LFSR components. Theoretical modeling together with insertion loss measurements provide the basis for a comprehensive power budget, which accounts for transmitted output power, transmission-line losses, antenna coupling, and plasma effects. Results indicate that high signal-to-noise ratios are achievable with the current design. A synthetic reflectometer model, using real design parameters and baseline ITER profiles, has been developed to estimate the return signal. With evolving microwave and data acquisition technologies, full-band, ultrafast sweeps (<1 μs) will be realizable for ITER.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

DOE OSTI2022

100 Gb/s High Throughput Serial Protocol (HTSP) for data acquisition systems with interleaved streaming

Demands on Field-Programmable Gate Array (FPGA) data transport have been increasing over the years as frame sizes and refresh rates increase. As the bandwidths requirements increase the ability to implement data transport protocol layers using "soft" programmable logic becomes harder and start to require harden IP blocks implementation. To reduce the number of physical links and interconnects, it is common for data acquisition systems to require interleaving of streams on the same link (e.g. streaming data and streaming register access). Further, this paper presents a way to leverage existing FPGA harden IP blocks to achieve a robust, low latency 100 Gb/s point-to-point link with minimal programmable logic overhead geared towards the needs of data acquisition systems with interleaved streaming requirements.

47 OTHER INSTRUMENTATION↗

DOE OSTI2026

High-bandwidth frequency domain multiplexed readout of transition-edge sensors for neutrinoless double beta decay searches

The next-generation of cryogenic neutrinoless double-beta decay experiments require increasingly fast readout in order to improve background discrimination. These experiments, operated as cryogenic calorimeters at ∼ 10 mK, are usually read out by high-impedance neutron transmutation doped (NTD) thermistors, which provide good energy resolution, but are limited by ∼ 1 ms response times. Superconducting detectors, such as transition-edge sensors (TESs) with a time resolution of ∼ 100 μs, offer superior timing performance over NTD semiconductor bolometers. To make this technology viable for an application to a thousand or more channels, multiplexed readout is necessary in order to minimize the thermal load and radioactive contamination induced by the readout. Frequency-domain multiplexing readout (fMUX) for TESs, previously developed at Berkeley Lab and McGill University, is currently in use for mm-wave telescopes with detector sampling rates in the order of 100 Hz. We demonstrate a new readout system, based on the McGill/Berkeley digital fMux readout, to satisfy the higher bandwidth and noise requirements of the next generation of TES-instrumented cryogenic calorimeters. Each multiplexing readout module comprises 10 superconducting resonators in the 1–5 MHz range and a DC superconducting quantum interference device (DC-SQUID), interfaced to high-speed field programmable gate array (FPGA)-based electronics for digital signal processing and low-latency SQUID feedback. The new readout samples detectors at 156 kHz, three orders of magnitude faster than its cosmology-oriented predecessor, and demonstrates a stable feedback bandwidth of 3 kHz in a real TES-based system.

47 OTHER INSTRUMENTATION↗

DOE OSTI2026

Gaia: segmented germanium detector for high-energy X-ray fluorescence and spectroscopic imaging

We present Gaia, a monolithic array of 96 high-purity germanium pixel detectors integrated with a custom low-noise application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA)-based data acquisition system. The sensor operates at ∼100 K using a commercial closed-cycle cryocooler, with the in-vacuum electronics thermally isolated from the cold finger to ensure thermal stability. The system demonstrates an average energy resolution of 711 eV at 122 keV, measured using a 57 Co source, and 253 eV at 5.89 keV, measured with 55 Fe across all channels. The readout architecture incorporates a high-performance FPGA paired with a dual-core ARM processor, forming a complete embedded Linux-based computing platform. Communication between the processor and FPGA is handled via memory-mapped I/O, and data are streamed over high-speed gigabit Ethernet. A full-scale 384-pixel Gaia detector, based on this 96-element module, is currently under fabrication.

36 MATERIALS SCIENCE↗

DOE OSTI2019

Single-Submodule Open-Circuit Fault Diagnosis for a Modular Multi-level Converter Using Artificial Intelligent-based Techniques

Modular multi-level converters (MMCs) are one of the promising topologies in recent years for medium or high voltage applications. They are considered as the next generation DC/AC converters for medium/high voltage (MV/HV) motor drive applications due to their transform-less structures, high efficiency and modularity. Reliability is one of the most important challenges in MMCs, since a large number of power switching devices are used and each of these devices can be considered as a potential failure point. It is significant to detect and locate the fault accurately and apply appropriate protections in a timely manner. This paper investigates the behavior of the failure submodules and healthy submodules and use artificial neural network (ANN) classification algorithms for singlesubmodule open-circuit fault diagnosis. The ANN algorithm is implemented in field programmable gate array (FPGA) and the ANN parameters training is completed offline in Matlab. Experimental results of the proposed fault diagnosis for a singlemodule open-circuit fault are presented in this paper.

artificial intelligent↗

DOE OSTI2019

OPEN-CODE, REAL-TIME EMULATION TESTBED OF GRID-CONNECTED TYPE-3 WIND TURBINE SYSTEM WITH HARDWARE VALIDATION

This paper presents the design and development of an open-code Type-3 wind turbine virtual-testbed for real-time simulations. The proposed testbed includes the bare code for all the models required to emulate a Type-3 wind turbine system: the Doubly-Fed Induction Generator (DFIG) dynamic model, single-mass drive train, wind turbine system, and average model of the back to back power. This testbed can be executed in PC-layer for offline simulations or can be executed in real-time on the National Instruments (NI)-CompactRIO (cRIO) platform. The discrete-time models are implemented on the Field Programmable Gate Array (FPGA), using LabVIEW, and validated against a physical hardware setup. The emulated stator and rotor currents and DC-link voltage are compared against physical measurements creating a validated platform independent from third-party models and suitable for applications in real-time. The proposed testbed is intended to be available to researchers, wind turbine manufacturers, and utility companies to perform tests using a validated platform to verify proposed control designs of DFIG wind turbines.

Ferrari Maglia, Max↗

DOE OSTI2018

Advanced Photovoltaic Inverter Control Development and Validation in a Controller-Hardware-in-the-Loop Test Bed

Penetration of solar photovoltaic (PV) installations into the grid has increased in recent years. In the past, photovoltaic installations have not included grid-support functionality. Grid support functions including Volt-VAR (VVAR), Frequency-Watt (FW), Volt-Watt (VW), frequency/voltage-ride through, as well as other inverter functions such as anti-islanding are recommended by standards such as IEEE 1547 to allow PV inverters to contribute to acceptable operation and stability of distribution systems with high penetrations of PV and to ensure predictable response of the PV inverters. First, low-level and high-level grid support inverter control functions were developed and tested in simulation. The developed controller is able to integrate advanced controller functions in a coordinated approach, avoiding any conflict between the different control objectives. The algorithms were then programmed on an off-the-shelf embedded controller that included a dual-core CPU and FPGA. The details of the high-level grid support function and the lower level switching control will be presented. Second, this programmed controller is tested using a controller-hardware-in-the-loop (CHIL) test bed setup using an FPGA-based real-time simulator. The CHIL setup has the capability to run at a 500 nano-second time-step to accommodate the 20 kHz switching frequency of the developed controller. The advanced control function and CHIL test bed details provided here will aide future researchers to design, implement, and test advanced inverter functions for PV inverters.

14 SOLAR ENERGY↗

DOE OSTI2022

Power Electronic Hardware-in-the-Loop (PE-HIL): Testing Individual Controllers in Large-Scale Power Electronics Systems

Large power electronics systems like multi-port autonomous reconfigurable solar power plant (MARS) are increasingly being researched upon to integrate emerging energy sources. MARS connects photovoltaic (PV) systems and energy storage systems (ESSs) to high-voltage direct current (HVdc) links/grids and high-voltage alternating current (ac) transmission grids. As these large power electronics systems incorporate complex hierarchical control systems that are close-by and communicate fast, the control systems require an unique power electronic hardware-in-the-loop (PE-HIL) real-time architecture to evaluate individual controllers. In this paper, a PE-HIL real-time architecture is proposed to evaluate one of the hundreds to thousands of digital signal processors (DSPs) that are a part of the complex hierarchical control system. The DSP connects to a central processing unit (CPU) and a field programmable gate array (FPGA) that form a part of the upper levels of the control system. The DSP is part of the lower level of the control system. The proposed PE-HIL architecture is tested and evaluated. Preliminary test results are presented to showcase the concept.

Debnath, Suman↗

DOE OSTI2023

Machine Learning Models for Network Traffic Classification in Programmable Logic

Network traffic classification via machine learning on network packet payloads has emerged as an active area of research for network security due to the high accuracy machine learning models have achieved in classifying payloads. For effective deployment as part of network security, these machine learning models must not only classify malicious packet payloads accurately, they must also identify anomalous payloads and perform inference at speeds generally faster than 10,000 packets per second to be effective. This work explores the in- ference speeds and accuracy of several neural network models implemented in programmable logic on various field programmable gate arrays (FPGA) including the Xilinx VC1902 and Xilinx Zynq Ultrascale+. This work also presents the design and performance of both an autoencoder and variational autoencoder programmed on the FPGA for identifying anomalous packet payloads. The performance benefits of the FPGA implementation for this type of packet payload inspection driven by machine learning are compared against graphics processing unit (GPU) inference implementations run on two state-of-the-art datacenter GPU devices, the NVIDIA V100 and A100. The model accuracy difference between the FPGA and GPU implementations was found to be 4% or less while the Xilinx VC1902 outperformed both the NVIDIA V100 and A100 for inference speeds on all the models explored except the variational autoencoder.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Two-Layer Predictive Controller for V2G and G2V Services Using on Wireless Power Transfer Technology

This paper presents a comprehensive solution that allows electric vehicles (EV) to autonomously charge and discharge their batteries wirelessly during long term parking and/or the transient stops. A two-layer power-flow controller for bidirectional wireless power transfer system (BWPTS) in EVs applications is proposed. The proposed controller can manage the bidirectional power-flow between EV and surrounding infrastructures such as power grid, home microgrid, building micro-grid, road or another vehicle. It consists of two levels of control; the first is responsible for communicating with the surrounding infrastructures and gathering information from driver, charging station, power grid and battery management system and then, based on these information, it estimates the EV's psychological price as a function of its battery's state-of-charge (SOC) and compares it with the energy price to decide whether to charge, discharge or abstain, and how much the charging or discharging rate. The second layer receives the reference signal from the first one and generates the control parameters for two synchronized resonant converters (one is on the vehicle side and the other is on the grid side) to provide the requited power-flow. The proposed controller is adaptively estimating the system parameters to consider the misalignment conditions effects on the system performance. The parameter estimation is achieved using only one voltage sensor. The second layer control is designed based on a new analytical modeling for the power flow in the system. For verification purposes, a prototype for BWPTS was built and driven by the proposed controller, which was implemented using a field-programmable gate array (FPGA) integrated circuit. The proposed controller provides very fast and stable response during both the transient and steady state operation in comparison with the conventional PI controller.

33 ADVANCED PROPULSION SYSTEMS↗

DOE OSTI2024

Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering

Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training method, we generate compact SNN models with 91% signal efficiency, akin to convolutional neural networks but with half the parameters. However, deploying near the detector poses a challenge because the SNN must handle a sustained input data rate exceeding 1013 GB/s. To overcome this, we propose a novel hardware architecture that uses high-level synthesis to construct a tuned architecture for the EONS-trained SNN. In addition to the analysis and validation with an AMD Xilinx Artix-A7 FPGA, our solution consumes only ç24% of FPGA LUT and flipflops. We also introduce an innovative quantization method that reduces FPGA resource utilization by ç15% without compromising accuracy. Our FPGA implementation achieves computing latency of ç10 ns for smart-pixel application inference on an edge FPGA.

Miniskar, Narasinga Rao↗

DOE OSTI2017

Noise Radar Approach for Interrogating SAW Sensors Using Software Defined Radio

Passive, wireless surface acoustic wave (SAW) sensor systems can be approached from a radar perspective, where the SAW device is thought of as a cooperative target. Here, this paper investigates the use of a commercial-off-the-shelf software defined radio to interrogate wireless SAW sensors with a randomly generated interrogation pulse. The USRP B200mini is utilized as the transceiver platform with custom field-programmable gate array (FPGA) modifications to generate the random interrogation waveform and provide synchronization and buffering to the received signal. Each transmit sample bit in the FPGA is fed by an independent linear-feedback shift register, which generates pseudo-random I and Q samples for the interrogation pulse. An RF daughterboard has also been developed and integrated with the B200mini to increase the transmit power, provide filtering of the RF signals, and switch a signal antenna between the transmit and receive channels. Radio control and matched filter correlator post-processing are accomplished using Python. Design and implementation details for the FPGA modifications, RF daughterboard, and post-processing are discussed. Lastly, the system is demonstrated by wirelessly interrogating SAW temperature sensors at 915 MHz.

47 OTHER INSTRUMENTATION↗

DOE OSTI2018

Comparison of Doubly-Fed Induction Generator Machine Models for Real-Time Simulations

This work presents a detailed comparison among three implementations of the Doubly-Fed Induction Generator (DFIG) machine model. The alpha-beta-gamma, synchronous (dqo), and natural frame dynamic machine models were deployed on a Field-Programmable Gate Array (FPGA) and compared in terms of execution time and resource utilization. These machine models were also validated against a physical DFIG machine during balanced and unbalanced grid conditions. A benchmark is presented with the objective of selecting the machine model, orientation and state-space representation that is best suited for real-time simulations. The selected machine model is used to develop a real-time emulator of a Type-3 wind system. This emulator enables the study of wind turbine system in realtime using a validated platform while allowing controller testing without relying on expensive third-party solutions.

Ferrari Maglia, Max↗

DOE OSTI2020

IEEE 1547-2018 Based Interoperable PV Inverter with Advanced Grid-Support Functions

Grid integration of photovoltaic (PV) inverters has been increasing in the past decade. As a result of the uncertainties introduced with high penetrations of PV, better monitoring and control of the PV inverters becomes crucial for improving overall system stability. This paper focuses on the communications capability of the inverter controller and on enabling interoperability. Multiple standards are available to enable interoperability in PV inverters. In this paper, an interoperable controller, enabled by Distributed Network Protocol 3 (DNP3) communications protocols, is developed for a grid-connected, three-phase PV inverter. The DNP3 server for the PV inverter is programmed on the real-time layer of the field-programmable gate array (FPGA)-based inverter controller. Set points for advanced inverter control functions, such as volt/VAr curves, ride-through curves, are sent from a DNP3 client, a simulated distribution management system application, to the PV inverter through DNP3. This communications capability of the inverter controller is validated using a controller-hardware-in-the-loop experimental setup. The code developed to achieve the interoperability is available in the public domain through open-source software licensing. This interoperability will enable smoother grid integration of smart PV inverters with advanced grid-support functions as well as allow better monitoring and control of PV inverters for grid stability.

14 SOLAR ENERGY↗

DOE OSTI2016

Development of ROACH firmware for microwave multiplexed X-ray TES microcalorimeters

We are developing room temperature electronics based upon the ROACH platform for reading out microwave multiplexed X-ray TES. ROACH is an open-source hardware and software platform featuring a large Xilinx Field Programmable Gate Array (FPGA), Power PC processor, several 10GB Ethernet SFP+ interfaces, and a collection of daughter boards for analog signal generation and acquisition. The combination of a ROACH board, ADC/DAC conversion daughter boards, and hardware for RF mixing allows for the generation and capture of multiple RF tones for reading out microwave multiplexed x-ray TES microcalorimeters. The FPGA is used to generate multiple tones in base band, from 10MHz to 250MHz, which are subsequently mixed to RF in the multiple GHz range and sent through the microwave multiplexer. The tones are generated in the FPGA by storing a large lookup table in Quad Data Rate (QDR) SRAM modules and playing out the waveform to a DAC board. Once the signal has been modulated to RF, passed through the microwave multiplexer, and has been modulated back to base band, the signal is digitized by an ADC board. The tones are modulated to 0Hz by using a FPGA circuit consisting of a polyphase filter bank, several Xilinx FFT blocks, Xilinx CORDIC blocks (for converting to magnitude and phase), and special phase accumulator circuit for mixing to exactly 0Hz. Upwards of 256 channels can be simultaneously captured and written into a bank of 256 First-In-First-Out (FIFO) memories, with each FIFO corresponding to a channel. Individual channel data can be further processed in the FPGA before being streamed through a 10GB Ethernet fiber-optic interface to a Linux system. The Linux system runs software written in Python and QT C++ for controlling the ROACH system, capturing data, and processing data.

Firmware↗

DOE OSTI2013

Design of the Trigger Interface and Distribution Board for TJNAF 12 GeV Upgrade

The design of the Trigger Interface and Distribution (TID) board for the 12 GeV Upgrade at Thomas Jefferson National Accelerator Facility (TJNAF) is described. The TID board distributes a low jitter system clock, synchronized trigger, and synchronized multi-purpose SYNC signal. The TID also initiates readout for the data acquisition front-end crate. With the TID boards, a multi-crate system can be setup for large scale nuclear physics experiments. The TID board can be selectively populated as a Trigger Interface (TI) board, or a Trigger Distribution (TD) board for the 12 GeV upgrade experiments. When the TID is populated as a TI, The TID can be located in the VXS crate and distribute the CLOCK/TRIGGER/SYNC (CTS) through the VXS/P0 connector; it can also be located in the standard VME64 crate, and distribute the CTS through the VME/P2 connector or front panel connectors. It initiates the data acquisition for the front-end crate where the TI is positioned in. When the TID is populated as a TD, it fans out the CTS from the trigger supervisor to the front-end crates through optical fibres. The TD board monitors the trigger processing on the TI boards, and sends feedback to the Trigger Supervisor (TS) board for event readout flow control. A Field Programmable Gate Arrays (FPGA) is utilised on the TID board to provide programmability. The TID board was intensively tested on the bench. The TID production version has been released to industry for contract manufacturing.

Gu, Jianhui W.↗