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NASA NTRS1993

NASA Space Engineering Research Center for VLSI System Design

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

Source record↗

NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗

NASA NTRS1993

Automated radiation hard ASIC design tool

A commercial based, foundry independent, compiler design tool (ChipCrafter) with custom radiation hardened library cells is described. A unique analysis approach allows low hardness risk for Application Specific IC's (ASIC's). Accomplishments, radiation test results, and applications are described.

White, Mike↗

NASA NTRS1993

Macro, mini, micro and nano (M(sup 3)N) technologies for the future

Microelectromechanical systems (MEMS), micro systems technologies (MST), and micromanufacturing are relatively recent phrases or acronyms that have become synonymous with the design, development, and manufacture of 'micro' devices and systems. Micromanufacturing encompasses MEMS or MST and, in addition, includes all of the processes involved in the production of micro things. Integration of mechanical and electrical components, including built-in computers, can be formed into systems which must be connected to the macroworld. Macro, mini, micro, and nano technologies are all a part of MEMS or micromanufacturing. At this point in the development of the technology, it is becoming apparent that mini systems, with micro components, could very well be the economic drivers of the technology for the foreseeable future. Initial research in the fabrication of microdevices using IC processing technology took place over thirty years ago. Anisotropic etching of silicon was used to produce piezoresistive diaphragms. Since the early 60's, there has been gradual progress in MEMS until the early 1980's when worldwide interest in the technology really started to develop. During this time high aspect ratio micromachining using x rays was started in Germany. In 1987 the concept of a 'silicon micromechanics foundry' was proposed. Since then the interest in the U.S., Germany, and Japan has increased to the point where hundreds of millions of dollars of research monies are being funneled into the technology (at least in Germany and Japan) and the technology has been classified as critical or as a technology or national importance by the U.S. government.

Friedrich, Craig R.↗

NASA NTRS1994

The future of large format HgCdTe arrays for astronomy

Rockwell has developed the 256 x 256 Near Infrared Camera and Multi-Object Spectrometer 3 (NICMOS3) FPA for the Hubble Space Telescope under funding from NASA through the University of Arizona. Since 1989, dozens of science grade devices have been delivered to astronomers throughout the world for ground based infrared observations. These devices have excellent sensitivity at 77 K with mean dark currents of 0.1 e(-)/s, noise of 25 e(-), and quantum efficiency of 55-70%. Pixel yields as high as 99.9% have been achieved. Our present plans are to develop a 1024 x 1024 focal plane array (FPA) with 2.5 micron cutoff and make it available to astronomers. Such large arrays are made possible by the advances in detector material size (3 in. diameter producible alternative to CdTe for epitaxy (PACE-I) wafers), multiplexer advances (ability to verify the design in detail and availability of advanced foundries), and novel hybridization and reliability approaches.

Vural, K.↗

NASA NTRS1995

Computed Tomography For Internal Inspection Of Castings

Computed tomography used to detect internal flaws in metal castings before machining and otherwise processing them into finished parts. Saves time and money otherwise wasted on machining and other processing of castings eventually rejected because of internal defects. Knowledge of internal defects gained by use of computed tomography also provides guidance for changes in foundry techniques, procedures, and equipment to minimize defects and reduce costs.

Hanna, Timothy L.↗

NASA NTRS1995

Wide field imaging of solar system objects with an 8192 x 8192 CCD mosaic

As part of this program, we successfully completed the construction of the world's largest CCD camera, an 8192 x 8192 CCD mosaic. The system employs 8 2K x 4K 3-edge buttable CCDs arranged in a 2 x 4 chip mosaic. The focal plane has small gaps (less than 1 mm) between mosaic elements and measures over 120 mm x 120 mm. The initial set of frontside illuminated CCDs were developed with Loral-Fairchild in a custom foundry run. The initial lots yielded of order 20 to 25 functional devices, of which we selected the best eight for inclusion for the camera. We have designed a custom 3-edge-buttable package that ensures the CCD dies are mounted flat to plus or minus 10 microns over the entire area of the mosaic. The mosaic camera system consists of eight separate readout signal chains controlled by two independent DSP microcontrollers. These are in turn interfaced to a Sun Sparc-10 workstation through two high speed fiber optic interfaces. The system saw first-light on the Canada-France-Hawaii Telescope on Mauna Kea in March 1995. First-light on the University of Hawaii 2.2-M Telescope on Mauna Kea was in July 1995. Both runs were quite successful. A sample of some of the early science from the first light run is reported in the publication, 'Observations of Weak Lensing in Clusters with an 8192 x 8192 CCD Mosaic Camera'.

Hall, Donald N. B.↗

NASA NTRS2000

Highly Parallel Computing Architectures by using Arrays of Quantum-dot Cellular Automata (QCA): Opportunities, Challenges, and Recent Results

There has been significant improvement in the performance of VLSI devices, in terms of size, power consumption, and speed, in recent years and this trend may also continue for some near future. However, it is a well known fact that there are major obstacles, i.e., physical limitation of feature size reduction and ever increasing cost of foundry, that would prevent the long term continuation of this trend. This has motivated the exploration of some fundamentally new technologies that are not dependent on the conventional feature size approach. Such technologies are expected to enable scaling to continue to the ultimate level, i.e., molecular and atomistic size. Quantum computing, quantum dot-based computing, DNA based computing, biologically inspired computing, etc., are examples of such new technologies. In particular, quantum-dots based computing by using Quantum-dot Cellular Automata (QCA) has recently been intensely investigated as a promising new technology capable of offering significant improvement over conventional VLSI in terms of reduction of feature size (and hence increase in integration level), reduction of power consumption, and increase of switching speed. Quantum dot-based computing and memory in general and QCA specifically, are intriguing to NASA due to their high packing density (10(exp 11) - 10(exp 12) per square cm ) and low power consumption (no transfer of current) and potentially higher radiation tolerant. Under Revolutionary Computing Technology (RTC) Program at the NASA/JPL Center for Integrated Space Microelectronics (CISM), we have been investigating the potential applications of QCA for the space program. To this end, exploiting the intrinsic features of QCA, we have designed novel QCA-based circuits for co-planner (i.e., single layer) and compact implementation of a class of data permutation matrices, a class of interconnection networks, and a bit-serial processor. Building upon these circuits, we have developed novel algorithms and QCA-based architectures for highly parallel and systolic computation of signal/image processing applications, such as FFT and Wavelet and Wlash-Hadamard Transforms.

Fijany, Amir↗

NASA NTRS2000

Application of Rapid Prototyping to the Investment Casting of Test Hardware (MSFC Center Director's Discretionary Fund Final Report, Project No. 98-08)

Investment casting masters of a selected propulsion hardware component, a fuel pump housing, were rapid prototyped on the several processes in-house, along with the new Z-Corp process acquired through this project. Also, tensile samples were prototyped and cast using the same significant parameters. The models were then shelled in-house using a commercial grade zircon-based slurry and stucco technique. Next, the shelled models were fired and cast by our in-house foundry contractor (IITRI), with NASA-23, a commonly used test hardware metal. The cast models are compared by their surface finish and overall appearance (i.e., the occurrence of pitting, warping, etc.), as well as dimensional accuracy.

Cooper, K. G.↗

NASA NTRS1997

A Low Cost Rad-Tolerant Standard Cell Library

This paper describes circuit design techniques developed at the NASA Institute of Advanced Microelectronics that have been shown to protect CMOS circuits from the deleterious effects of the natural space radiation environment. The IAuE is leading a program to incorporate these radiation-tolerance providing design techniques into a commercial standard cell library that will be used in conjunction with available Electronic Design Automation tools to produce space flight qualified microelectronics fabricated at modern commercial CMOS foundries.

Gambles, Jody W.↗

NASA NTRS2002

Benefits Awareness: Educating Industry, Finance, and the Public About Space Commercialization

For space to be truly commercialized, businesses of all sizes and types must be involved, from foundries to agricultural research initiatives. Achieving this goal, however, requires three separate but integrated educational efforts to support it. The first is to educate industry leaders about the possibilities available through such research, while dispelling some of the myths and misinformation educate the financial community about the economic benefits that result both from the research and the leveraging of private research dollars through the use of space and microgravity research. The third is to educate the public about the tangible benefits that come directly to them from such efforts, the economic benefits to national economies from same, and the other less tangible benefits that will cascade from commercial operations. Together, these steps will educate and provide the framework necessary to help advance space commercialization.

Powers, Blake↗

NASA NTRS1996

Highly Efficient Amplifier for Ka-Band Communications

An amplifier developed under a Small Business Innovation Research (SBIR) contract will have applications for both satellite and terrestrial communications. This power amplifier uses an innovative series bias arrangement of active devices to achieve over 40-percent efficiency at Ka-band frequencies with an output power of 0.66 W. The amplifier is fabricated on a 2.0- by 3.8-square millimeter chip through the use of Monolithic Microwave Integrated Circuit (MMIC) technology, and it uses state-of-the-art, Pseudomorphic High-Electron-Mobility Transistor (PHEMT) devices. Although the performance of the MMIC chip depends on these high-performance devices, the real innovations here are a unique series bias scheme, which results in a high-voltage chip supply, and careful design of the on-chip planar output stage combiner. This design concept has ramifications beyond the chip itself because it opens up the possibility of operation directly from a satellite power bus (usually 28 V) without a dc-dc converter. This will dramatically increase the overall system efficiency. Conventional microwave power amplifier designs utilize many devices all connected in parallel from the bias supply. This results in a low-bias voltage, typically 5 V, and a high bias current. With this configuration, substantial I(sup 2) R losses (current squared times resistance) may arise in the system bias-distribution network. By placing the devices in a series bias configuration, the total current is reduced, leading to reduced distribution losses. Careful design of the on-chip planar output stage power combiner is also important in minimizing losses. Using these concepts, a two-stage amplifier was designed for operation at 33 GHz and fabricated in a standard MMIC foundry process with 0.20-m PHEMT devices. Using a 20-V bias supply, the amplifier achieved efficiencies of over 40 percent with an output power of 0.66 W and a 16-dB gain over a 2-GHz bandwidth centered at 33 GHz. With a 28-V bias, a power level of 1.1 W was achieved with a 12-dB gain and a 36-percent efficiency. This represents the best reported combination of power and efficiency at this frequency. In addition to delivering excellent power and gain, this Ka-band MMIC power amplifier has an efficiency that is 10 percent greater than existing designs. The unique design offers an excellent match for spacecraft applications since the amplifier supply voltage is closely matched to the typical value of spacecraft bus voltage. These amplifiers may be used alone in applications of 1 W or less, or several may be combined or used in an array to produce moderate power, Ka-band transmitters with minimal power combining and less thermal stress owing to the combination of excellent efficiency and power output. The higher voltage operation of this design may also save mass and power because the dc-dc power converter is replaced with a simpler voltage regulator.

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NASA NTRS2003

Superalloy Lattice Block Developed for Use in Lightweight, High-Temperature Structures

Successful development of advanced gas turbine engines for aircraft will require lightweight, high-temperature components. Currently titanium-aluminum- (TiAl) based alloys are envisioned for such applications because of their lower density (~4 g/cm3) in comparison to superalloys (~8.5 g/cm3), which have been utilized for hot turbine engine parts for over 50 years. However, a recently developed concept (lattice block) by JAMCORP, Inc., of Willmington, Massachusetts, would allow lightweight, high-temperature structures to be directly fabricated from superalloys and, thus, take advantage of their well-known, characterized properties. In its simplest state, lattice block is composed of thin ligaments arranged in a three dimensional triangulated trusslike configuration that forms a structurally rigid panel. Because lattice block can be fabricated by casting, correctly sized hardware is produced with little or no machining; thus very low cost manufacturing is possible. Together, the NASA Glenn Research Center and JAMCORP have extended their lattice block methodology for lower melting materials, such as Al alloys, to demonstrate that investment casting of superalloy lattice block is possible. This effort required advances in lattice block pattern design and assembly, higher temperature mold materials and mold fabrication technology, and foundry practice suitable for superalloys (ref. 1). Lattice block panels have been cast from two different Ni-base superalloys: IN 718, which is the most commonly utilized superalloy and retains its strength up to 650 C; and MAR M247, which possesses excellent mechanical properties to at least 1100 C. In addition to the open-cell lattice block geometry, same-sized lattice block panels containing a thin (~1-mm-thick) solid face on one side have also been cast from both superalloys. The elevated-temperature mechanical properties of the open cell and face-sheeted superalloy lattice block panels are currently being examined, and the microstructure is being characterized in terms of casting defects. In addition, a small study (ref. 3) is being undertaken with GE Aircraft Engines to determine the suitability of superalloy lattice block for engine components.

Hebsur, Mohan G.↗

NASA NTRS2005

A New Large-Well 1024x1024 Si:As Detector for the Mid-Infrared

We present a description of a new 1024x1024 Si:As array designed for ground-based use from 5 - 28 microns. With a maximum well depth of 5e6 electrons, this device brings large-format array technology to bear on ground-based mid-infrared programs, allowing entry to the mega-pixel realm previously only accessible to the near-IR. The multiplexer design features switchable gain, a 256x256 windowing mode for extremely bright sources, and it is two-edge buttable. The device is currently in its final design phase at DRS in Cypress, CA. We anticipate completion of the foundry run in October 2005. This new array will enable wide field, high angular resolution ground-based follow up of targets found by space-based missions such as the Spitzer Space Telescope and the Wide-field Infrared Survey Explorer (WISE).

astronomy↗

NASA NTRS2006

Repairing Chipped Silicide Coatings on Refractory Metal Substrates

The space shuttle orbiter s reaction control system (RCS) is a series of small thrusters that use hypergolic fuels to orient the orbiter in space. The RCS thrusters are constructed from a special niobium-based alloy -- the C-103. This alloy retains excellent mechanical properties from cryogenic temperature all the way up to 2,500 F (1,370 C). C-103 is susceptible to rapid oxidation at elevated temperatures. The authors have developed two methods to repair damaged R512a coatings on C-103. For the first repair technique, metal foundries, semiconductor manufacturers, and many other industries have developed and routinely use coatings that can easily be painted on metal to protect it from corrosion, including oxidation, to temperatures in excess of 2,500 F (1,370 C). This first repair technique is considered somewhat temporary. The second repair technique is based on using the native coating material of the RCS nozzles. the chipped area is ground out and a "green" R512a coating is applied to the repair area. Both repair techniques can be applied for moderate protection until the permanent laser-repair technique is available to the repair area.

Youngquist, Robert↗

NASA NTRS2011

Nanoscale Deformable Optics

Several missions and instruments in the conceptual design phase rely on the technique of interferometry to create detectable fringe patterns. The intimate emplacement of reflective material upon electron device cells based upon chalcogenide material technology permits high-speed, predictable deformation of the reflective surface to a subnanometer or finer resolution with a very high degree of accuracy. In this innovation, a layer of reflective material is deposited upon a wafer containing (perhaps in the millions) chalcogenic memory cells with the reflective material becoming the front surface of a mirror and the chalcogenic material becoming a means of selectively deforming the mirror by the application of heat to the chalcogenic material. By doing so, the mirror surface can deform anywhere from nil to nanometers in spots the size of a modern day memory cell, thereby permitting realtime tuning of mirror focus and reflectivity to mitigate aberrations caused elsewhere in the optical system. Modern foundry methods permit the design and manufacture of individual memory cells having an area of or equal to the Feature (F) size of the design (assume 65 nm). Fabrication rules and restraints generally require the instantiation of one memory cell to another no closer than 1.5 F, or, for this innovation, 90 nm from its neighbor in any direction. Chalcogenide is a semiconducting glass compound consisting of a combination of chalcogen ions, the ratios of which vary according to properties desired. It has been shown that the application of heat to cells of chalcogenic material cause a large alteration in resistance to the range of 4 orders of magnitude. It is this effect upon which chalcogenidebased commercial memories rely. Upon removal of the heat source, the chalcogenide rapidly cools and remains frozen in the excited state. It has also been shown that the chalcogenide expands in volume because of the applied heat, meaning that the coefficient of expansion of chalcogenic materials is larger than 1. In this innovation, chalcogenidebased cells are addressed (as though they are a memory), and heated and cooled according to well-established criteria. In doing so, the exact size of chalcogenide cell deformation is known and predictable; therefore, the deformation of the reflective surface is, likewise, known and predictable. Control electronics can also be implemented so that a closed-loop feedback can be maintained. Changing the contents of the chalcogenide memory cells can compensate for any change in environmental effects that might cause a change in optical path. This real-time control provides significant control and stability in use conditions.

Strauss, Karl F.↗

NASA NTRS2005

Improved Method of Manufacturing SiC Devices

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Okojie, Robert S.↗

NASA NTRS2005

Improvements in Fabrication of Sand/Binder Cores for Casting

Three improvements have been devised for the cold-box process, which is a special molding process used to make sand/binder cores for casting hollow metal parts. These improvements are: The use of fiber-reinforced composite binder materials (in contradistinction to the non-fiber-reinforced binders used heretofore), The substitution of a directed-vortex core-blowing subprocess for a prior core-blowing process that involved a movable gassing plate, and The use of filters made from filtration-grade fabrics to prevent clogging of vents. For reasons that exceed the scope of this article, most foundries have adopted the cold-box process for making cores for casting metals. However, this process is not widely known outside the metal-casting industry; therefore, a description of pertinent aspects of the cold-box process is prerequisite to a meaningful description of the aforementioned improvements. In the cold-box process as practiced heretofore, sand is first mixed with a phenolic resin (considered to be part 1 of a three-part binder) and an isocyanate resin (part 2 of the binder). Then by use of compressed air, the mixture is blown into a core box, which is a mold for forming the core. Next, an amine gas (part 3 of the binder) that acts as a catalyst for polymerization of parts 1 and 2 is blown through the core box. Alternatively, a liquid amine that vaporizes during polymerization can be incorporated into the sand/resin mixture. Once polymerization is complete, the amine gas is purged from the core box by use of compressed air. The finished core is then removed from the core box.

Bakhitiyarov, Sayavur I.↗