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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Tri-gate GaN junction HEMT

This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 10 8 . Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (V TH ) and achieve positive V TH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) > 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. Finally, these results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Report on High Energy Arcing Fault Experiments: Experimental Results from Low-Voltage Switchgear Enclosures

This report documents an experimental program designed to investigate High Energy Arcing Fault (HEAF) phenomena for low-voltage metal enclosed switchgear containing aluminum conductors. This report covers full-scale laboratory experiments using representative nuclear power plant (NPP) three-phase electrical equipment. Electrical, thermal, and pressure data were recorded for each experiment and documented in this report. This report covers experiments performed on two low-voltage switchgear units with each unit consisting of two vertical sections. The data collected supports characterization of the low-voltage HEAF hazard and these results will be used to support potential improvements in fire probabilistic risk assessment (PRA) methods. The experiments were performed at KEMA Labs located in Chalfont, Pennsylvania. The experimental design, setup, and execution were completed by staff from the NRC, the National Institute of Standards and Technology (NIST), Sandia National Laboratories (SNL) and KEMA. In addition, representatives from the Electric Power Research Institute (EPRI) observed some of the experimental setup and execution. The HEAF experiments were performed between August 26 and Augsut 29, 2019 on nearidentical Westinghouse Type DS low-voltage metal-enclosed indoor switchgear. The threephase arcing fault was initiated on the aluminum main bus or in select cases on the copper bus stabs near the breaker. These experiments used either nominal 480 volts AC or 600 volts AC. Durations of the experiments ranged from approximately 0.4 s to 8.3 s with fault currents ranging from approximately 9.2 kA to 19.3 kA. Real-time electrical operating conditions, including voltage, current and frequency, were measured during the experiments. Heat fluxes and incident energies were measured with plate thermometers, radiometers, and slug calorimeters at various locations around the electrical enclosures. Environmental measurements of breakdown, conductivity and electromagnetics were also taken. The experiments were documented with normal and high-speed videography, infrared imaging and photography. The results, while limited, indicated the difficulty in maintaining and sustaining low-voltage arcs on aluminum components of sufficient duration and at a single point as observed operating experience.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2021

Imaging of Electrothermal Filament Formation in a Mott Insulator

Resistive switching—the current- and voltage-induced change of electrical resistance—is at the core of memristive devices, which play an essential role in the emerging field of neuromorphic computing. This study is about resistive switching in a Mott insulator, which undergoes a thermally driven metal-to-insulator transition. Two distinct switching mechanisms are reported for such a system: electric-field-driven resistive switching and electrothermal resistive switching. The latter results from an instability caused by Joule heating. Here, we present the visualization of the reversible resistive switching in a planar V 2 O 3 thin-film device using high-resolution wide-field microscopy in combination with electric transport measurements. We investigate the interaction of the electrothermal instability with the strain-induced spontaneous phase separation in the V 2 O 3 thin film at the Mott transition. The photomicrographs show the formation of a narrow metallic filament with a minimum width ≲500 nm. Although the filament formation and the overall shape of the current-voltage characteristics (IVCs) are typical of an electrothermal breakdown, we also observe atypical effects such as oblique filaments, filament splitting, and hysteretic IVCs with sawtoothlike jumps at high currents in the low-resistance regime. We are able to reproduce the experimental results in a numerical model based on a two-dimensional resistor network. This model demonstrates that resistive switching in this case is indeed electrothermal and that the intrinsic heterogeneity is responsible for the atypical effects. This heterogeneity is strongly influenced by strain, thereby establishing a link between switching dynamics and structural properties.

42 ENGINEERING↗
DOE OSTI2025

Enhancement-Mode GaN Monolithic Bidirectional Switch With Breakdown Voltage Over 3.3 kV

Here, this work demonstrates a GaN enhancement-mode monolithic bidirectional switch (MBDS) with breakdown voltage (BV) higher than 3.3 kV in both polarities. This MBDS is realized on a dual p-GaN gate high electron mobility transistor (HEMT) platform on sapphire substrate. It features a novel dual junction termination extension design for electric field management, which is built on the p-GaN layer in the gate stack and does not require epitaxial regrowth. The GaN MBDS exhibits symmetric on-state characteristics in both directions with a threshold voltage (V th ) of 0.6 V and a low specific on-resistance (R on,sp ) of 5.6 m Ω · cm2. This device presents the highest BV, as well as one of the best BV and R on,sp trade-offs, in all the reported MBDS devices. The R on,sp is lower than the performance limit of conventional BDS realized by two discrete devices. This 3.3 kV GaN MBDS opens the door for developing new circuit topologies and advancing system performance in medium-voltage power electronics.

42 ENGINEERING↗
DOE OSTI2023

High-performance HZO/InAlN/GaN MISHEMTs for Ka-band application

This paper reports on the demonstration of microwave power performance at 30 GHz on InAlN/GaN metal–insulator–semiconductor high electron mobility transistor (MISHEMT) on silicon substrate by using the Hf 0.5 Zr 0.5 O 2 (HZO) as a gate dielectric. Compared with Schottky gate HEMT, the MISHEMT with a gate length (L G ) of 50 nm presents a significantly enhanced performance with an ON/OFF current ratio (I ON /I OFF ) of 9.3 × 10 7 , a subthreshold swing of 130 mV dec -1 , a low drain-induced barrier lowing of 45 mV V -1 , and a breakdown voltage of 35 V. RF characterizations reveal a current gain cutoff frequency (f T ) of 155 GHz and a maximum oscillation frequency (f max ) of 250 GHz, resulting in high (f T × f max ) 1/2 of 197 GHz and the record high Johnson's figure-of-merit (JFOM = f T × BV) of 5.4 THz V among the reported GaN MISHEMTs on Si. Further, the power performance at 30 GHz exhibits a maximum output power of 1.36 W mm -1 , a maximum power gain of 12.3 dB, and a peak power-added efficiency of 21%, demonstrating the great potential of HZO/InAlN/GaN MISHEMTs for the Ka-band application.

42 ENGINEERING↗
DOE OSTI2024

Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage ( V DS_SAT ) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance ( R ON ), and a higher V DS_SAT . Here, the challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in V DS_SAT is demonstrated, wherein it reduces from >12 to 5 V.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Mitigating the Effects of Au-Al Intermetallic Compounds Due to High-Temperature Processing of Surface-Electrode Ion Traps

Stringent physical requirements need to be met for the high-performing surface-electrode ion traps used in quantum computing and timekeeping. In particular, these traps must survive a high-temperature environment for vacuum chamber preparation and support high RF voltage on closely spaced electrodes. Due to the use of gold wire bonds on aluminum pads, intermetallic growth can lead to wire bond failure via breakage or high resistance, limiting the lifetime of a trap assembly to a single multiday bake at 200 ° C. Using traditional thick metal stacks to prevent intermetallic growth, however, can result in trap failure due to RF breakdown events. Through high-temperature experiments, we conclude that an ideal metal stack for ion traps is Ti/Pt/Au (20/100/250 nm), which allows for a cumulative bakeable time of roughly 86 days without compromising the trap voltage performance. This increase in the bakeable lifetime of ion traps will remove the need to discard otherwise functional ion traps when vacuum hardware is upgraded, which will greatly benefit ion trap experiments.

Haltli, Raymond A.↗
DOE OSTI2023

Integration of Ultrawide Bandgap Photoconducting Semiconductor Switches into High-Voltage, High-Current Pulser Systems

In this feasibility study we will evaluate the viability of integrating ultrawide bandgap (UWBG) photoconducting semiconductor switches (PCSS) in high-voltage pulser systems capable of driving low-impedance dynamic loads critical for next-generation accelerator and RF-source applications. The project consisted of developing modelling tools that would inform design of UWBG PCSS packages that could be mounted onto conventional circuit boards. Specifically, we are interested in evaluating the following through simulation software: (1) resistance to electrical breakdown (2) proximity effects due to high-frequency skin effect (3) transient behavior from switching (4) effective transmission of RF signals (5) thermal dynamics of the switch under operation (6) sensitivity to inhomogeneities in optical excitation of the material (7) cross-talk effects from parallel switching structures, and (8) susceptibility of system to damaged components. The project resulted in the development of a special-purpose circuit code that implements photoconductivity physics. This code was used to evaluate objectives 1-6 above, identifying a critical requirement associated with the need for fine control of dopant concentrations in the UWBG material to reach an optimal solution for voltage standoff and laser light responsivity requirements. In addition, we identified that the temperature dependence of the electrical conductivity of this material was typically not well-measured and developed a platform for measuring both the “dark” and “illuminated” conductivity on real physical switches in the lab to better inform our models.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Structural Instability in Electrically Stressed, Oxygen Deficient BaTiO 3 Nanocrystals

The dynamics of oxygen vacancies under external stimuli dominates the performance of many solid-state devices, including capacitors, oxide memristors, anionic conductors, etc. By means of in-situ Transmission Electron Microscopy, we found in BaTiO 3 perovskite nanocrystals that formation of oxygen vacancies due to electrical stressing renders the oxide amorphizable under electron beam illumination, suggesting the presence of a threshold concentration of oxygen vacancy affecting the structural stability of BaTiO 3 crystals upon high energy radiation. In contrast to the structural change, the resistivity of the nanocrystal seems not liable to the amorphization prior to dielectric breakdown at higher voltage bias. Here, we propose that an increase in oxygen vacancy content promotes oxygen mobility in the perovskite structure allowing electron beam induced electric field to modify the local structural and composition. Our in-situ observations reveal the central role of oxygen vacancies in the structural stability of perovskites which is of paramount importance to their applications in extreme environments and suggest a potential new route to micro-processing perovskite oxides using the electron beam via oxygen vacancy management without severely compromising the electric property.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Impact of metal diffusion, lattice distortions, native defects, and ambient on dielectric breakdown in Ni–Ga 2 O 3 Schottky diodes

Ga 2 O 3 unipolar devices are of high interest due to their ~8 MV/cm predicted breakdown fields, which have not yet been achieved due to premature device failure. Pre- and post-failure defect analysis of Ni–Ga 2 O 3 Schottky diodes in ultrahigh vacuum (UHV) and air were performed using depth-resolved cathodoluminescence, high angle annular dark field scanning transmission electron microscopy, and energy dispersive x-ray analysis to understand the physical mechanisms that precede premature breakdown. The breakdown voltage in UHV was dramatically reduced by nearly 40% compared with the breakdown in air. This reduction in the breakdown voltage correlated with post-breakdown differences in Ni distribution, indicating that the coordination and bonding of Ni contribute strongly to electrical behavior in Ni–Ga 2 O 3 Schottky diodes. Breakdown studies in UHV revealed that Ni diffuses away more from the metal–semiconductor interface than with air breakdown, where Ni localizes more near the interface, indicative of the preferential formation of a Ni oxide under O-poor conditions. These measurements also identified the formation of divacancy-interstitial complexes and their characteristic luminescence signature ~150 nm from the interface, the densities of which correlated with breakdown fields. These findings show that electric-field-induced degradation occurs via the rearrangement of native point defects, which act as an additional precursor to device failure. Macroscopically, they show the impact of both vacuum conditions and metal reactivity on Ga 2 O 3 device fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Building the next high voltage dc photogun polarized source for the ILC at JLab

During the ILC Global Design Effort (2007) two 200 kV high voltage photoguns based on an inverted insulator geometry were developed in 2010 and successfully tested at Jefferson Lab (JLab). One of the photoguns has been operated at 130 kV in the CEBAF accelerator for the JLab nuclear physics program. The inverted insulator replaces the electrode support structure, consequently significantly less metal prone to field emission is biased and surfaces contributing to the vacuum load are significantly reduced. Implementing a biased anode, and using a larger laser spot size has made this the state of the art polarized beam source with ~200 C charge lifetime from SSL GaAs photocathodes. However, operating at the design 200 kV voltage has been hindered by field emission at ~190 kV. To reliably operate without field emission requires lengthy conditioning applying 50-100 kV beyond the voltage needed for beam operations, without breakdown or damage to the insulator. Over the past decade, JLab has developed two photoguns with a larger version of the commercial inverted insulators used in the ILC design. One photogun operated at 300 kV for magnetized beam studies, and the concept has been implemented in the BNL polarized photogun. The second photogun has recently been installed in CEBAF to operate at 200 kV field emission free. Higher voltage photoguns help the ILC and CLIC achieve higher bunch charge (2013 TDR), and additionally provide margin for operating with shorter laser pulse length and/or smaller laser spot size (better emittance at higher peak current). Such photogun designs need to reach ~400 kV without breakdown or insulator damage to operate field emission free at > 300 kV. This also allows for direct injection into a SRF booster. JLab submitted a proposal to HEP for developing in partnership with industry an inverted geometry insulator to fit commercial 400 kV cables. This contribution describes JLab experience developing and testing high voltage photoguns, and what is needed to sufficiently condition for voltage levels higher than beam operational voltage.

Hernandez-Garcia, Carlos↗
DOE OSTI2022

Breakdown of the $v=1$ integer quantum Hall effect in the single particle and collective localization regimes

We report large signal current–voltage characteristics measurements near the $v=1$ integer quantum Hall plateau in a high mobility GaAs/AlGaAs sample that exhibits both single particle and collective localization. According to prior results, the central part of the $v=1$ plateau corresponds to single particle localization and hence an Anderson insulator. In contrast, the two regions in the flanks of this Anderson insulator were associated with collective localization and were identified with the integer quantum Hall Wigner solid. We find that, at low temperatures and under large bias currents, both the Anderson insulator and integer quantum Hall Wigner solid have a sharp onset of conduction above a threshold. Furthermore, this threshold shows an approximately monotonic dependence on the filling factor across the boundary between the two localized phases. Finally, to our surprise, we find that these large signal characteristics do not clearly distinguish between the Anderson insulator and the integer quantum Hall Wigner solid.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

1.2-kV Vertical GaN PIN Rectifier With Ion-Implanted Floating Guard Rings

Here, this work reports on the fabrication and properties of a homojunction gallium nitride (GaN) p-i-n (PIN) rectifier fabricated on a free-standing GaN substrate. Uniform device performance is achieved with breakdown voltage (BV) >1.2 kV and low ON-resistance × area ( R ON A ). The statistics of the BV measurements show 58.5% of devices achieve BV >1.3 kV, and 71.1% of devices achieve BV >1.2 kV, as attributed to high quality and control in both epitaxial growth and device process. At room temperature, R ON A is 0.23 mΩ∙ cm 2 at a current density ( J ) of 6.9 kA/cm2. The corresponding Baliga’s figure of merit is >5.97 GW/cm 2 . Temperature-dependent reverse I – V measurements were performed and show a positive temperature coefficient of 0.42 V/K, indicating the avalanche capability of reverse breakdown. Further analysis with the Poole-Frenkel model on the temperature-dependent measurement suggested that a trap-assisted tunneling process contributed to the reverse leakage current. Floating guard rings (FGRs) formed by nitrogen implantation serve as an effective edge termination technique in these GaN PIN rectifiers, resulting in uniform performance in both forward and reverse bias.

42 ENGINEERING↗
DOE OSTI2022

β -Ga 2 O 3 Schottky barrier diodes with 4.1 MV/cm field strength by deep plasma etching field-termination Available

In this work, we demonstrate a deep mesa etch design for efficient edge field termination in β-Ga 2 O 3 Schottky barrier diodes (SBDs). The proposed design enabled parallel plate fields higher than 4.1 MV/cm with negligible change to the device ON characteristics. The effect of BCl 3 /Cl 2 -based dry etch on (100) and (010) etched vertical sidewalls is also analyzed. A remarkable anisotropy in depletion was observed for etch along (100) and (010) sidewalls. In conclusion, this work provides insight into the impact of etching on n-type Ga 2 O 3 and shows a promising method to realize efficient field termination for high breakdown field strength SBDs.

42 ENGINEERING↗
DOE OSTI2025

Robust Avalanche (1.5 kV, 2 kA/cm²) in Vertical GaN Diodes on Patterned Sapphire Substrate

The lack of avalanche capability is a key limitation of current lateral GaN devices. Despite the report of avalanche in vertical GaN-on-GaN devices, the high wafer cost hinders device commercialization. Here, in this work, we demonstrate a circuit-level avalanche in vertical GaN diodes on low-cost patterned sapphire substrate (PSS), with the avalanche voltage (1.57 kV) and avalanche current density (>2 kA/cm 2 ) both being the highest reported in GaN devices on foreign substrates. The PSS enables a lower dislocation density than conventional sapphire substrate and is employed in high-voltage GaN devices for the first time. The avalanche voltage in the circuit test reaches 98% of the parallel-plane limit, further affirming that near-ideal avalanche breakdown can be realized on GaN devices on foreign substrates. These results show the promise of the GaN-on-PSS platform for low-cost, robust power devices.

42 ENGINEERING↗
DOE OSTI2020

HVDC Surface Flashover in Compressed Air for Various Dielectrics

Here, this study measures the voltage at which flashover occurs in compressed air for a variety of dielectric materials and lengths in a uniform field for DC voltages up to 100 kV. Statistical time lag is recorded and characterized, displaying a roughly exponential dependence on breakdown voltage. Of the materials tested, acrylic is observed to be the most resistant to flashover. These data are intended to facilitate the design of compressed-air insulated high voltage systems as an alternative to SF 6 insulated systems.

42 ENGINEERING↗
DOE OSTI2021

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) using plasma deposited BN as gate dielectric

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) were fabricated on Si substrates with a 10 nm boron nitride (BN) layer as a gate dielectric deposited by electron cyclotron resonance microwave plasma chemical vapor deposition. The material characterization of the BN/GaN interface was investigated by X-ray photoelectric spectroscopy (XPS) and UV photoelectron spectroscopy. The BN bandgap from the B1s XPS energy loss is ~5 eV consistent with sp2 bonding. The MISHEMTs exhibit a low off-state current of 1 × 10 –8 mA/mm, a high on/off current ratio of 10 9 , a threshold voltage of –2.76 V, a maximum transconductance of 32 mS/mm at a gate voltage of –2.1 V and a drain voltage of 1 V, a subthreshold swing of 69.1 mV/dec, and an on-resistance of 12.75 Ω·mm. The interface state density (D it ) is estimated to be less than 8.49 × 10 11 cm –2 eV –1 . Gate leakage current mechanisms were investigated by temperature-dependent current–voltage measurements from 300 K to 500 K. The maximum breakdown electric field is no less than 8.4 MV/cm. Poole–Frenkel emission and Fowler–Nordheim tunneling are indicated as the dominant mechanisms of the gate leakage through the BN gate dielectric at low and high electric fields, respectively.

36 MATERIALS SCIENCE↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗