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At least 91 records · Page 5

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NASA NTRS1982

Interconnect fatigue design for terrestrial photovoltaic modules

The results of comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable (1) the prediction of cumulative interconnect failures during the design life of an array field, and (2) the unambiguous--ie., quantitative--interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field.

Mon, G. R.↗

NASA NTRS1994

Reconfigurable optical interconnections via dynamic computer-generated holograms

A system is proposed for optically providing one-to-many irregular interconnections, and strength-adjustable many-to-many irregular interconnections which may be provided with strengths (weights) w(sub ij) using multiple laser beams which address multiple holograms and means for combining the beams modified by the holograms to form multiple interconnections, such as a cross-bar switching network. The optical means for interconnection is based on entering a series of complex computer-generated holograms on an electrically addressed spatial light modulator for real-time reconfigurations, thus providing flexibility for interconnection networks for largescale practical use. By employing multiple sources and holograms, the number of interconnection patterns achieved is increased greatly.

Liu, Hua-Kuang↗

NASA NTRS1996

Reconfigurable Optical Interconnections Via Dynamic Computer-Generated Holograms

A system is presented for optically providing one-to-many irregular interconnections, and strength-adjustable many-to-many irregular interconnections which may be provided with strengths (weights) w(sub ij) using multiple laser beams which address multiple holograms and means for combining the beams modified by the holograms to form multiple interconnections, such as a cross-bar switching network. The optical means for interconnection is based on entering a series of complex computer-generated holograms on an electrically addressed spatial light modulator for real-time reconfigurations, thus providing flexibility for interconnection networks for large-scale practical use. By employing multiple sources and holograms, the number of interconnection patterns achieved is increased greatly.

Liu, Hua-Kuang↗

NASA NTRS2004

Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the design and construction of a test setup for the experiment and then appropriate characterization of the test system. Specifically, I am involved in the characterization of a commercially available 1550nm wavelength, 5mW diode laser and a study of its modulation bandwidth. Commercially produced photodetectors as well as the incorporation of microwave technology, in the form of RF input and output, are used in the characterization procedure. The next stage involves the use of a probe station and network analyzer to characterize and test a series of photodetectors fabricated on a 2 inch, Indium Gallium Arsenide (InGaAs) wafer in the Branch s microlithography lab. Other project responsibilities include, but are not limited to the incorporation of a transimpedance amplifier to the photodetector circuit; a study of VCSEL technology; bit error rate analysis of an optical interconnect system; and analysis of free space divergence of the VCSEL, optical path length of the interconnect; and any other pertinent optical properties of the one gigabit per second interconnect for fabrication and testing.

Savich, Gregory R.↗

NASA NTRS2001

Zee electrical interconnect

An interconnect, having some length, that reliably connects two conductors separated by the length of the interconnect when the connection is made but in which one length if unstressed would change relative to the other in operation. The interconnect comprises a base element an intermediate element and a top element. Each element is rectangular and formed of a conducting material and has opposed ends. The elements are arranged in a generally Z-shape with the base element having one end adapted to be connected to one conductor. The top element has one end adapted to be connected to another conductor and the intermediate element has its ends disposed against the other end of the base and the top element. Brazes mechanically and electrically interconnect the intermediate element to the base and the top elements proximate the corresponding ends of the elements. When the respective ends of the base and the top elements are connected to the conductors, an electrical connection is formed therebetween, and when the conductors are relatively moved or the interconnect elements change length the elements accommodate the changes and the associated compression and tension forces in such a way that the interconnect does not mechanically fatigue.

Rust, Thomas M.↗

DOE OSTI2017

Fast process flow, on-wafer interconnection and singulation for MEPV

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

36 MATERIALS SCIENCE↗

DOE OSTI2017

Fast process flow, on-wafer interconnection and singulation for MEPV

36 MATERIALS SCIENCE↗

DOE OSTI2022

High-voltage push to mate electrical interconnect

A high-voltage self-aligning push to mate electrical interconnect device is provided. The electrical interconnect device includes a housing with a mating end and a receiving end. The interconnect also includes an insulator bushing configured to be affixed to the receiving end of the housing. The interconnect also includes a center pin disposed within the housing. The center pin extends from the mating end of the housing to the receiving end of the housing. The interconnect also includes a connector socket disposed within the insulator bushing and which is in electrical communication with the center pin. The interconnect also includes an alignment sleeve including a chamfered mating funnel defining a void configured to accept and surround the housing and at least a portion of insulator bushing.

Martinez, David K.↗

DOE OSTI2018

Failure stress comparison of different pairings of Ag-plating and reflow-oven-processed pressureless-sintered-Ag interconnects

Here, sintered-silver is a candidate material to supplant solders for interconnects in power electronic packaging for many reasons including its desirably high electrical and thermal conductivities and compliance to Restriction of Hazardous Substances (RoHS) guidelines. The shear failure stress of interconnects though is limited by whatever constituent is the weakest, and that includes any employed plating. In the present study, silver-platings were processed electrolytically, electrolessly, and through sputter deposition and their influence on the entire “interconnect system” shear strength was examined. Test sets employing gold plating and no plating were included for comparison and to aid interpretation. Ambient-air, reflow-oven-processed, pressureless-sintered-silver interconnects were identically fabricated with all plating test sets. It was found that all considered silver-plating methods produced consistently strong (characteristic failure stresses > 55 MPa) sintered-silver interconnects. Because failures tended to be adhesive in all six sets, differences in failure stress among the silver-plated sets and the gold-plated or unplated sets were likely due to differences in the adhesive strength of the sintered silver with silver-plating, gold-plating, or direct bonding with copper.

36 MATERIALS SCIENCE↗

DOE OSTI2019

Ferritic stainless steel interconnects for protonic ceramic electrochemical cell stacks: Oxidation behavior and protective coatings

Protonic ceramic fuel or electrolysis cells (PCFC/PCEC) have shown promising performance at intermediate temperatures. However, these technologies have not yet been demonstrated in a stack, hence the oxidation behavior of the metallic interconnect under relevant operating environments is unknown. In this work, ferritic stainless steels 430 SS, 441 SS, and Crofer 22 APU were investigated for their use as interconnect materials in the PCFC/PCEC stack. Specifically, the bare metal sheets were exposed to a humidified air environment in the temperature range from 450 °C to 650 °C, to simulate their application in a PCFC cathode or PCEC anode. Breakaway oxidation with rapid weight gain and Fe outward diffusion/oxidation was observed on all the selected stainless steel materials. A protective coating is deemed necessary to prevent the metallic interconnect from oxidizing. To mitigate the observed breakaway oxidation, state-of-the-art protective coatings, Y 2 O 3 , Ce 0.02 Mn 1.49 Co 1.49 O 4 , CuMn 1.8 O 4 and Ce/Co, were applied to the stainless steel sheets and their oxidation resistance was investigated. Dual atmosphere testing further validated the effectiveness of the protective coatings in realistic PCFC/PCEC environments, with a hydrogen gradient across the interconnect. Several combinations of metal and coating material were found to be viable for use as the interconnect for PCFC/PCEC stacks.

25 ENERGY STORAGE↗

DOE OSTI2022

Supervised Learning for Distribution Secondary Systems Modeling: Improving Solar Interconnection Processes

The current interconnection process and hosting capacity analysis for distributed energy resources (DERs), such as photovoltaics (PV) and battery energy storage systems, are based on analyzing grid network constraints (voltage and thermal) using only medium-voltage distribution network models. This is because most utilities do not have secondary low-voltage system models that connect service transformers and residential customers. This is important because in many cases the main impact of interconnecting DERs could occur on the low-voltage distribution systems. This paper proposes a supervised learning method to approximate local secondary models to improve the interconnection process. The proposed supervised learning method includes a decision tree model that predicts the secondary topology and a logistic regression model that predicts conductor types. The case studies demonstrate the benefits of including secondary low-voltage circuits in the interconnection process. We report the proposed modeling methodology is readily scalable and thus can reduce the cost and effort of PV interconnection for the industry and stakeholders.

14 SOLAR ENERGY↗

DOE OSTI2020

Nanometal-Interconnected Carbon Conductors (NICCS) for Advanced Electric Machines (RIT Final Technical Report)

Recent advancements in carbon nanotube (CNT) research have enabled lightweight, conductive wires as a transformative technology. Metal-carbon nanotube (CNT) hybrid conductors aim to combine the high conductivity of traditional metals with the low mass and temperature coefficient of resistance (TCR) of carbon nanotubes. The high conductivity of copper makes it a promising candidate to combine with CNTs in a hybrid structure, but there is limited physical and electrical interaction between copper and CNTs. The use of an interfacial layer offers one method of improving the interconnection of a Cu-CNT hybrid conductor. Over the course of this grant, a joule heating-driven chemical vapor deposition (CVD) technique was developed to deposit nanometal seeds throughout a porous, low-density (0.12 g/cm 3 , ~10 tex or mg/m) CNT roving template. Modification of the applied current to the CNT roving allows for the tuning of depositions towards either hot-spot site-specificity or overall uniformity. The effects of temperature, pressure, precursor mass, and the interval of applied current were investigated, demonstrating nanometal depositions ranging from less than 5 % w/w to over 85 % w/w. The versatility of CVD allows for a wide variety of metals to be deposited including copper, titanium, nickel, silver, tungsten, palladium, platinum, ruthenium, rhodium, and iridium. One preferred demonstration involved using platinum depositions to improve the electrical properties of metal-seeded CNTs across all mass loadings studied. Moreover, when the metal-seeded CNT wires were electroplated with copper, densified, and annealed under hydrogen/argon; the result was a Cu-CNT hybrid conductor with the highest conductivities reported to date. The good interconnection of the metal and CNT portions results in a stable conductor. An electrical conductivity of 16-20 MS/m was achieved for multiple Cu-CNT hybrid conductors at 150 °C, which exceeds the program goal for conductivity of greater than 15 MS/m for a 1 m long CNT wire. Overall, the research outcomes from the project showed improvements in CNT wire fabrication from roll-to-roll CVD grown carbon nanotube wires using nanometal interconnects to bridge CNT-to-CNT junctions, thus mitigating network contact resistances. Advanced nanometal interconnected carbon conductors (NICCs) were developed as a means to achieve novel light-weight wiring appropriate for applications that require the conductivity of metallic (i.e., Cu, Al, etc.) wires at elevated temperatures. High conductivity, low TCR electrical conductors such as the nanometal interconnected Cu-CNT hybrids have numerous future applications towards high efficiency motors, generators, and transformers. Specifically, the advanced wires have the ability to operate at lower resistance during conditions for standard electric motors at 150 °C, which would improve the electrical efficiency while lowering energy needs.

36 MATERIALS SCIENCE↗

DOE OSTI2024

Multi‐Objective Optimization for Rapid Identification of Novel Compound Metals for Interconnect Applications

Abstract Interconnect materials play the critical role of routing energy and information in integrated circuits. However, established bulk conductors, such as copper, perform poorly when scaled down beyond 10 nm, limiting the scalability of logic devices. Here, a multi‐objective search is developed, combined with first‐principles calculations, to rapidly screen over 15,000 materials and discover new interconnect candidates. This approach simultaneously optimizes the bulk electronic conductivity, surface scattering time, and chemical stability using physically motivated surrogate properties accessible from materials databases. Promising local interconnects are identified that have the potential to outperform ruthenium, the current state‐of‐the‐art post‐Cu material, and also semi‐global interconnects with potentially large skin depths at the GHz operation frequency. The approach is validated on one of the identified candidates, CoPt, using both ab initio and experimental transport studies, showcasing its potential to supplant Ru and Cu for future local interconnects.

Chemistry↗

DOE OSTI2017

Chemically interconnected light-weight 3D-carbon nanotube solid network

Owing to the weak physical interactions such as van der Waals and π-π interactions, which hold nanotubes together in carbon nanotube (CNT) bulk structures, the tubes can easily slide on each other. In creating covalent interconnection between individual carbon nanotube (CNT) structures we saw remarkable improvements in the properties of their three-dimensional (3D) bulk structures. The creation of such nanoengineered 3D solid structures with improved properties and low-density remains one of the fundamental challenges in real-world applications. We also report the scalable synthesis of low-density 3D macroscopic structure made of covalently interconnected nanotubes using free-radical polymerization method after functionalized CNTs with allylamine monomers. The resulted interconnected highly porous solid structure exhibits higher mechanical properties, larger surface area and greater porosity than non-crosslinked nanotube structures. To gain further insights into the deformation mechanisms of nanotubes, fully atomistic reactive molecular dynamics simulations are used. Here we demonstrate one such utility in CO 2 uptake, whose interconnected solid structure performed better than non-interconnected structures.

36 MATERIALS SCIENCE↗

DOE OSTI2018

Impact of pore size, interconnections, and dynamic conductivity on the electrochemistry of vanadium pentoxide in well defined porous structures

Considering the tortuous, random porous nanostructures existing in many battery electrodes, it is essential to understand electronic and ionic behaviors in such a confined nanoscale porous geometry in which electron and ion transports can change dynamically. Here, we have carefully designed three dimensional (3D) interconnected porous electrode structures and performed experiments to probe how the ion and electron transport is impacted within these controlled geometries. By using anodized aluminum oxide as a template, we were able to fabricate both 1D array electrodes and 3D electrodes with varying numbers of interconnections, utilizing vanadium oxide (V 2 O 5 ) as the active material. We demonstrate that the inherent properties of the electrode material in combination with the structural properties of the electrodes can both positively and negatively impact electrochemical characteristics. Most notably, electrodes with seven interconnecting layers in their structure had 19.7% less capacity at 25C than electrodes with zero interconnecting layers, demonstrating the negative effect of interconnections combined with poor electronic conductivity of V 2 O 5 upon lithiation beyond one Li insertion. These results indicate that a careful consideration of the material and structural properties is needed for the design of high performance battery systems.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2016

1/f noise measurements for faster evaluation of electromigration in advanced microelectronics interconnections

The use of 1/f noise measurements is explored for the purpose of finding faster techniques for electromigration (EM) characterization in advanced microelectronic interconnects, which also enable a better understanding of its underlying physical mechanisms. Three different applications of 1/f noise for EM characterization are explored. First, whether 1/f noise measurements during EM stress can serve as an early indicator of EM damage. Second, whether the current dependence of the noise power spectral density (PSD) can be used for a qualitative comparison of the defect concentration of different interconnects and consequently also their EM lifetime t50. Third, whether the activation energies obtained from the temperature dependence of the 1/f noise PSD correspond to the activation energies found by means of classic EM tests. In this paper, the 1/f noise technique has been used to assess and compare the EM properties of various advanced integration schemes and different materials, as they are being explored by the industry to enable advanced interconnect scaling. More concrete, different types of copper interconnects and one type of tungsten interconnect are compared. The 1/f noise measurements confirm the excellent electromigration properties of tungsten and demonstrate a dependence of the EM failure mechanism on copper grain size and distribution, where grain boundary diffusion is found to be a dominant failure mechanism.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2016

Characterization of process-induced damage in Cu/low-k interconnect structure by microscopic infrared spectroscopy with polarized infrared light

Microscopic Fourier-transform infrared (FT-IR) spectra are measured for a Cu/low-k interconnect structure using polarized IR light for different widths of low-k spaces and Cu lines, and for different heights of Cu lines, on Si substrates. Although the widths of the Cu line and the low-k space are 70 nm each, considerably smaller than the wavelength of the IR light, the FT-IR spectra of the low-k film were obtained for the Cu/low-k interconnect structure. A suitable method was established for measuring the process-induced damage in a low-k film that was not detected by the TEM-EELS (Transmission Electron Microscope-Electron Energy-Loss Spectroscopy) using microscopic IR polarized light. Based on the IR results, it was presumed that the FT-IR spectra mainly reflect the structural changes in the sidewalls of the low-k films for Cu/low-k interconnect structures, and the mechanism of generating process-induced damage involves the generation of Si-OH groups in the low-k film when the Si-CH{sub 3} bonds break during the fabrication processes. The Si-OH groups attract moisture and the OH peak intensity increases. It was concluded that the increase in the OH groups in the low-k film is a sensitive indicator of low-k damage. We achieved the characterization of the process-induced damage that was not detected by the TEM-EELS and speculated that the proposed method is applicable to interconnects with line and space widths of 70 nm/70 nm and on shorter scales of leading edge devices. The location of process-induced damage and its mechanism for the Cu/low-k interconnect structure were revealed via the measurement method.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2018

Apparent Fracture Toughness of Pressureless Sintered Silver Interconnects

This study uses three-point flexural testing to estimate the room-temperature apparent fracture toughness ( K Ic_app ) of a pressureless sintered-silver interconnect - a candidate material for use in power electronic devices. The K Ic_app estimation occurs via work-of-fracture measurement of a chevron-shaped sintered-silver joint centrally located in an “interconnect bend test specimen”. The chevron-shape was stencil-printed on a silver (Ag)-plated direct bonded copper (DBC) substrate, mated to an Ag-plated DBC substrate, and then sintered. The chevron-shape, used for decades in fracture mechanics examinations and in standardized tests of monolithic materials, enables controlled stable crack initiation and propagation that are prerequisites for valid K Ic_app estimation. The employed combination of an interconnect bend test specimen and bend test method is robust and simple, enables a means for interpreting the resistance to crack growth and delamination in an interconnect, provides a dependable way to judge the efficacies of sintered-silver processing conditions, and ultimately supports process optimization of sintered-silver interconnects.

36 MATERIALS SCIENCE↗