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NASA NTRS2010

Electrically Variable Resistive Memory Devices

Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

Liu, Shangqing↗
NASA NTRS2006

FETs Based on Doped Polyaniline/Polyethylene Oxide Fibers

A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.

Theofylaktos, Noulie↗
NASA NTRS2010

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗
NASA NTRS2010

IXO-XMS LVSID Anti-Coincidence Detector

This document describes a high-TRL backup implementation of the anti-coincidence detector for the IXO/XMS instrument. The backup detector, hereafter referred to as the low-voltage silicon ionization detector (LVSID), has been successfully flown on Astro-E2 (Suzaku)/XRS and is currently being implemented, without significant changes, on the Astro-H/SXS instrument. The LVSID anti-coincidence detector on Astro-E2/XRS operated successfully for almost 2 years, and was not affected by the loss of liquid helium in that instrument. The LVSID continues to operate after almost 5 years on-orbit (LEO, 550 km) but with slightly increased noise following the expected depletion of solid Neon after 22 months. The noise of the device is increased after the loss of sNe due to thermally induced bias and readout noise. No radiation damage, or off-nominal affects have been observed with the LVSID on-orbit during the Astro-E2/XRS program. A detector die from the same fabrication run will be used on the Astro-H/SXS mission. The LVSID technology and cryogenic JFET readout system is thus TRL 9. The technology is described in detail in section 2. The IXO/XMS "backup-up" anti-coincidence detector is a small array of LVSID detectors that are almost identical to those employed for Astro -E2/XRS as described in this document. The readout system is identical and, infact would use the same design as the Astro -E2/XRS JFET amplifier module (19 channels) essentially without changes except for its mechanical mount. The changes required for the IXO/XMS LVSID array are limited to the mounting of the LVSID detectors, and the mechanical mounting of the JFET amplifier sub-assembly. There is no technical development needed for the IXO/XMS implementation and the technology is ready for detailed design-work leading to PDR. The TRL level is thus at least 6, and possibly higher. Characteristics of an IXO/XMS LVSID anti-co detector are given in Table 1 and described in detail in section 3.

Porter, Scott F.↗
NASA NTRS2010

Fiber-Coupled Planar Light-Wave Circuit for Seed Laser Control in High Spectral Resolution Lidar Systems

Precise laser remote sensing of aerosol extinction and backscatter in the atmosphere requires a high-power, pulsed, frequency doubled Nd:YAG laser that is wavelength- stabilized to a narrow absorption line such as found in iodine vapor. One method for precise wavelength control is to injection seed the Nd:YAG laser with a low-power CW laser that is stabilized by frequency converting a fraction of the beam to 532 nm, and to actively frequency-lock it to an iodine vapor absorption line. While the feasibility of this approach has been demonstrated using bulk optics in NASA Langley s Airborne High Spectral Resolution Lidar (HSRL) program, an ideal, lower cost solution is to develop an all-waveguide, frequency-locked seed laser in a compact, robust package that will withstand the temperature, shock, and vibration levels associated with airborne and space-based remote sensing platforms. A key technology leading to this miniaturization is the integration of an efficient waveguide frequency doubling element, and a low-voltage phase modulation element into a single, monolithic, planar light-wave circuit (PLC). The PLC concept advances NASA's future lidar systems due to its compact, efficient and reliable design, thus enabling use on small aircraft and satellites. The immediate application for this technology is targeted for NASA Langley's HSRL system for aerosol and cloud characterization. This Phase I effort proposes the development of a potassium titanyl phosphate (KTP) waveguide phase modulator for future integration into a PLC. For this innovation, the proposed device is the integration of a waveguide-based frequency doubler and phase modulator in a single, fiber pigtail device that will be capable of efficient second harmonic generation of 1,064-nm light and subsequent phase modulation of the 532 nm light at 250 MHz, providing a properly spectrally formatted beam for HSRL s seed laser locking system. Fabrication of the integrated PLC chip for NASA Langley, planned for the Phase II effort, will require full integration and optimization of the waveguide components (SHG waveguide, splitters, and phase modulator) onto a single, monolithic device. The PLC will greatly reduce the size and weight, improve electrical- to-optical efficiency, and significantly reduce the cost of NASA Langley s current stabilized HSRL seed laser system built around a commercial off-the-shelf seed laser that is free-space coupled to a bulk doubler and bulk phase modulator.

Cook, Anthony↗
NASA NTRS2010

Large-Format AlGaN PIN Photodiode Arrays for UV Images

A large-format hybridized AlGaN photodiode array with an adjustable bandwidth features stray-light control, ultralow dark-current noise to reduce cooling requirements, and much higher radiation tolerance than previous technologies. This technology reduces the size, mass, power, and cost of future ultraviolet (UV) detection instruments by using lightweight, low-voltage AlGaN detectors in a hybrid detector/multiplexer configuration. The solar-blind feature eliminates the need for additional visible light rejection and reduces the sensitivity of the system to stray light that can contaminate observations.

Aslam, Shahid↗
NASA NTRS2011

High-Voltage-Input Level Translator Using Standard CMOS

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Yager, Jeremy A.↗
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
NASA NTRS2011

Effect of Reverse Bias Stress on Leakage Currents and Breakdown Voltages of Solid Tantalum Capacitors

The majority of solid tantalum capacitors are produced by high-temperature sintering of a fine tantalum powder around a tantalum wire followed by electrolytic anodization that forms a thin amorphous Ta2O5 dielectric layer and pyrolysis of manganese nitrite on the oxide to create a conductive manganese dioxide electrode. A contact to tantalum wire is used as anode terminal and to the manganese layer as a cathode terminal of the device. This process results in formation of an asymmetric Ta -- Ta2O5 -- MnO2 capacitor that has different characteristics at forward (positive bias applied to tantalum) and reverse (positive bias applied to manganese cathode) voltages. Reverse bias currents might be several orders of magnitude larger than forward leakage currents so I-V characteristics of tantalum capacitors resemble characteristics of semiconductor rectifiers. Asymmetric I-V characteristics of Ta -- anodic Ta2O5 systems have been observed at different top electrode materials including metals, electrolytes, conductive polymers, and manganese oxide thus indicating that this phenomenon is likely related to the specifics of the Ta -- Ta2O5 interface. There have been multiple attempts to explain rectifying characteristics of capacitors employing anodic tantalum pentoxide dielectrics. A brief review of works related to reverse bias (RB) behavior of tantalum capacitors shows that the mechanism of conduction in Ta -- Ta2O5 systems is still not clear and more testing and analysis is necessary to understand the processes involved. If tantalum capacitors behave just as rectifiers, then the assessment of the safe reverse bias operating conditions would be a relatively simple task. Unfortunately, these parts can degrade with time under reverse bias significantly, and this further complicates analysis of the I-V characteristics and establishing safe operating areas of the parts. On other hand, time dependence of reverse currents might provide additional information for investigation of the processes under reverse bias conditions. In practice, there were instances when, due to unforeseen events, the system operated at conditions when capacitors experience periodically a relatively small reverse bias for some time followed by normal, forward bias conditions. In such a case an assessment should be made on the degree to which these capacitors are degraded by application of low-voltage reverse bias, and whether this degradation can be reversed by normal operating conditions. In this study, reverse currents in different types of tantalum capacitors were monitored at different reverse voltages below 15%VR and temperatures in the range from room to 145 C for up to 150 hours to get better understanding of the degradation process and determine conditions favorable to the unstable mode of operation. The reversibility of RB degradation has been evaluated after operation of the capacitors at forward bias conditions. The effect of reverse bias stress (RBS) on reliability at normal operating conditions was evaluated using highly accelerated life testing at voltages of 1.5VR and 2 VR and by analysis of changes in distributions of breakdown voltages. Possible mechanisms of RB degradation are discussed.

Teverovsky, Alexander A.↗
NASA NTRS2011

Development of Sample Verification System for Sample Return Missions

This paper describes the development of a proof of-concept sample verification system (SVS) for in-situ mass measurement of planetary rock and soil sample in future robotic sample return missions. Our proof-of-concept SVS device contains a 10 cm diameter pressure sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in proximity to an opposing substrate with a narrow gap. The deformation of the membrane makes the gap to be narrower, resulting in increased capacitance between the two nearly parallel plates. Capacitance readout circuitry on a nearby printed circuit board (PCB) transmits data via a low-voltage differential signaling (LVDS) interface. The fabricated SVS proof-of-concept device has successfully demonstrated approximately 1pF/gram capacitance change

Electrodes↗
NASA NTRS2004

Event-Driven Random-Access-Windowing CCD Imaging System

A charge-coupled-device (CCD) based high-speed imaging system, called a realtime, event-driven (RARE) camera, is undergoing development. This camera is capable of readout from multiple subwindows [also known as regions of interest (ROIs)] within the CCD field of view. Both the sizes and the locations of the ROIs can be controlled in real time and can be changed at the camera frame rate. The predecessor of this camera was described in High-Frame-Rate CCD Camera Having Subwindow Capability (NPO- 30564) NASA Tech Briefs, Vol. 26, No. 12 (December 2002), page 26. The architecture of the prior camera requires tight coupling between camera control logic and an external host computer that provides commands for camera operation and processes pixels from the camera. This tight coupling limits the attainable frame rate and functionality of the camera. The design of the present camera loosens this coupling to increase the achievable frame rate and functionality. From a host computer perspective, the readout operation in the prior camera was defined on a per-line basis; in this camera, it is defined on a per-ROI basis. In addition, the camera includes internal timing circuitry. This combination of features enables real-time, event-driven operation for adaptive control of the camera. Hence, this camera is well suited for applications requiring autonomous control of multiple ROIs to track multiple targets moving throughout the CCD field of view. Additionally, by eliminating the need for control intervention by the host computer during the pixel readout, the present design reduces ROI-readout times to attain higher frame rates. This camera (see figure) includes an imager card consisting of a commercial CCD imager and two signal-processor chips. The imager card converts transistor/ transistor-logic (TTL)-level signals from a field programmable gate array (FPGA) controller card. These signals are transmitted to the imager card via a low-voltage differential signaling (LVDS) cable assembly. The FPGA controller card is connected to the host computer via a standard peripheral component interface (PCI).

Monacos, Steve↗
NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗
NASA NTRS2011

Distributed Capacitive Sensor for Sample Mass Measurement

Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane.

Toda, Risaku↗
NASA NTRS2012

High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA

Analog-to-digital converters (ADCs) are used in scientific and communications instruments on all spacecraft. As data rates get higher, and as the transition is made from parallel ADC designs to high-speed, serial, low-voltage differential signaling (LVDS) designs, the need will arise to interface these in field programmable gate arrays (FPGAs). As Xilinx has released the radiation-hardened version of the Virtex-5, this will likely be used in future missions. High-speed serial ADCs send data at very high rates. A de-serializer instantiated in the fabric of the FPGA could not keep up with these high data rates. The Virtex-5 contains primitives designed specifically for high-speed, source-synchronous de-serialization, but as supported by Xilinx, can only support bitwidths of 10. Supporting bit-widths of 12 or more requires the use of the primitives in an undocumented configuration, a non-trivial task. A new SystemVerilog design was written that is simpler and uses fewer hardware resources than the reference design described in Xilinx Application Note XAPP866. It has been shown to work in a Xilinx XC5VSX24OT connected to a MAXIM MAX1438 12-bit ADC using a 50-MHz sample clock. The design can be replicated in the FPGA for multiple ADCs (four instantiations were used for a total of 28 channels).

Taylor, Gregory H.↗
NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗
NASA NTRS2012

SpaceCube Mini

This version of the SpaceCube will be a full-fledged, onboard space processing system capable of 2500+ MIPS, and featuring a number of plug-andplay gigabit and standard interfaces, all in a condensed 3x3x3 form factor [less than 10 watts and less than 3 lb (approximately equal to 1.4 kg)]. The main processing engine is the Xilinx SIRF radiation- hardened-by-design Virtex-5 FX-130T field-programmable gate array (FPGA). Even as the SpaceCube 2.0 version (currently under test) is being targeted as the platform of choice for a number of the upcoming Earth Science Decadal Survey missions, GSFC has been contacted by customers who wish to see a system that incorporates key features of the version 2.0 architecture in an even smaller form factor. In order to fulfill that need, the SpaceCube Mini is being designed, and will be a very compact and low-power system. A similar flight system with this combination of small size, low power, low cost, adaptability, and extremely high processing power does not otherwise exist, and the SpaceCube Mini will be of tremendous benefit to GSFC and its partners. The SpaceCube Mini will utilize space-grade components. The primary processing engine of the Mini is the Xilinx Virtex-5 SIRF FX-130T radiation-hardened-by-design FPGA for critical flight applications in high-radiation environments. The Mini can also be equipped with a commercial Xilinx Virtex-5 FPGA with integrated PowerPCs for a low-cost, high-power computing platform for use in the relatively radiation- benign LEOs (low-Earth orbits). In either case, this version of the Space-Cube will weigh less than 3 pounds (.1.4 kg), conform to the CubeSat form-factor (10x10x10 cm), and will be low power (less than 10 watts for typical applications). The SpaceCube Mini will have a radiation-hardened Aeroflex FPGA for configuring and scrubbing the Xilinx FPGA by utilizing the onboard FLASH memory to store the configuration files. The FLASH memory will also be used for storing algorithm and application code for the PowerPCs and the Xilinx FPGA. In addition, it will feature highspeed DDR SDRAM (double data rate synchronous dynamic random-access memory) to store the instructions and data of active applications. This version will also feature SATA-II and Gigabit Ethernet interfaces. Furthermore, there will also be general-purpose, multi-gigabit interfaces. In addition, the system will have dozens of transceivers that can support LVDS (low-voltage differential signaling), RS-422, or SpaceWire. The SpaceCube Mini includes an I/O card that can be customized to meet the needs of each mission. This version of the SpaceCube will be designed so that multiple Minis can be networked together using SpaceWire, Ethernet, or even a custom protocol. Scalability can be provided by networking multiple SpaceCube Minis together. Rigid-Flex technology is being targeted for the construction of the SpaceCube Mini, which will make the extremely compact and low-weight design feasible. The SpaceCube Mini is designed to fit in the compact CubeSat form factor, thus allowing deployment in a new class of missions that the previous SpaceCube versions were not suited for. At the time of this reporting, engineering units should be available in the summer 2012.

Michael Lin↗
NASA NTRS2012

Lidar Electro-Optic Beam Switch with a Liquid Crystal Variable Retarder

A document discusses a liquid crystal variable retarder, an electro-optic element that changes the polarization of an optical beam in response to a low-voltage electronic signal. This device can be fabricated so that the element creates, among other states, a half-wave of retardance that can be reduced to a very small retardance. When aligned to a polarized source, this can act to rotate the polarization by 90 in one state, but generate no rotation in the other state. If the beam is then incident on a polarization beam splitter, it will efficiently switch from one path to the other when the voltage is applied. The laser beam switching system has no moving parts, improving reliability over mechanical switching. It is low cost, tolerant of high laser power density, and needs only simple drive electronics, minimizing the required system resources.

Baer, James↗
NASA NTRS1995

STRV-1B Cryocooler Vibration Suppression

The STRV-1B cryocooler vibration suppression experiment is a satellite flight demonstration of piezo vibration-suppression technology. A very small, tactical stirling-cooler was flown primarily as a vibration source. Two types of piezo actuators were demonstrated. Low-voltage piezo translators were used to move the entire cryocooler so that the tip of the coldfinger stood still. Also, high-voltage ceramic applique was bonded to the base of the coldfinger providing a second actuation method to compare with the translators. three eddy current transducers were used to measure the coldfinger tip motion relative to the experiment case. The eddy current signal drove two types of control systems. A digital adaptive-feed- forward control system was used to cancel the tip motion of the cryocooler in three dimensions. An analog-comb filter controller was also developed to contrast the two techniques. Motion suppression does nothing to suppress the unbalanced forces in the cryocooler, so a triaxial accelerometer measured the vibration of the satellite in response to the cryocooler. Satellite/ground test results from each of the experiment systems are shown and the systems are compared.

STRV-1B↗