Search NASA⌕ Search

SEARCH · Search NASA

Results for “programmable”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 91 records · Page 5

Skyrmion-Based Programmable Logic Device with Complete Boolean Logic Functions

A skyrmionic programmable logic device (SkrPLD) with complete Boolean logic functions is proposed and analyzed by micromagnetic simulations. The SkrPLD is based on an antiferromagnet/ferromagnet bilayer structure, in which the antiferromagnetic layer supports the interfacial Dzyaloshinskii–Moriya interaction and the out-of-plane exchange bias field for stabilizing a zero-field skyrmion. By varying the local exchange bias field, artificial pinning sites are introduced for trapping the skyrmions. Depending on the input currents and the initial position of skyrmions at different pinning sites, different logic functions can be realized. Micromagnetic simulations show that the proposed SkrPLD has robust performance even under thermal fluctuations and inhomogeneity effects. Our work can provide insights for the design of programmable spin logic devices.

74 ATOMIC AND MOLECULAR PHYSICS↗

Experimental realization of classical Z 2 spin liquids in a programmable quantum device

We build and probe a Z 2 spin liquid in a programmable quantum device, the D-Wave DW-2000Q. Specifically, we observe the classical eight-vertex and six-vertex (spin ice) states and transitions between them. To realize this state of matter, we design a Hamiltonian with combinatorial gauge symmetry using only pairwise-qubit interactions and a transverse field, i.e., interactions which are accessible in this quantum device. The combinatorial gauge symmetry remains exact along the full quantum annealing path, landing the system onto the classical eight-vertex model at the endpoint of the path. The output configurations from the device allow us to directly observe the loop structure of the classical model. Moreover, we deform the Hamiltonian so as to vary the weights of the eight vertices and show that we can selectively attain the classical six-vertex (ice) model, or drive the system into a ferromagnetic state. Additionally, we present studies of the classical phase diagram of the system as a function of the eight-vertex deformations and effective temperature, which we control by varying the relative strengths of the programmable couplings, and we show that the experimental results are consistent with theoretical analysis. Finally, we identify additional capabilities that, if added to these devices, would allow us to realize Z 2 quantum spin liquids on which to build topological qubits.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.

97 MATHEMATICS AND COMPUTING↗

Online Convex Optimization of Programmable Quantum Computers to Simulate Time-Varying Quantum Channels

Simulating quantum channels is a fundamental primitive in quantum computing, since quantum channels define general (trace-preserving) quantum operations. An arbitrary quantum channel cannot be exactly simulated using a finite-dimensional programmable quantum processor, making it important to develop optimal approximate simulation techniques. In this paper, we study the challenging setting in which the channel to be simulated varies adversarially with time. We propose the use of matrix exponentiated gradient descent (MEGD), an online convex optimization method, and analytically show that it achieves a sublinear regret in time. Through experiments, we validate the main results for time-varying dephasing channels using a programmable generalized teleportation processor.

97 MATHEMATICS AND COMPUTING↗

Tweezer-programmable 2D quantum walks in a Hubbard-regime lattice

Quantum walks provide a framework for designing quantum algorithms that is both intuitive and universal. To leverage the computational power of these walks, it is important to be able to programmably modify the graph a walker traverses while maintaining coherence. We do this by combining the fast, programmable control provided by optical tweezers with the scalable, homogeneous environment of an optical lattice. With these tools we study continuous-time quantum walks of single atoms on a square lattice and perform proof-of-principle demonstrations of spatial search with these walks. When scaled to more particles, the capabilities demonstrated can be extended to study a variety of problems in quantum information science, including performing more effective versions of spatial search using a larger graph with increased connectivity.

Science & Technology - Other Topics↗

UPC++ v1.0 Programmer’s Guide, Revision 2020.10.0

UPC++ is a C++11 library that provides Partitioned Global Address Space (PGAS) programming. It is designed for writing parallel programs that run efficiently and scale well on distributed-memory parallel computers. The PGAS model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. However, PGAS also provides access to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ provides numerous methods for accessing and using global memory. In UPC++, all operations that access remote memory are explicit, which encourages programmers to be aware of the cost of communication and data movement. Moreover, all remote-memory access operations are by default asynchronous, to enable programmers to write code that scales well even on hundreds of thousands of cores.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Programmer’s Guide, Revision 2021.9.0

UPC++ is a C++ library that provides Partitioned Global Address Space (PGAS) programming. It is designed for writing parallel programs that run efficiently and scale well on distributed-memory parallel computers. The PGAS model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. PGAS additionally provides one-sided Remote Memory Access (RMA) to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ also features Remote Procedure Call (RPC) communication, making it easy to move computation to operate on data that resides on remote processes. In UPC++, all communication operations are explicit, which encourages programmers to be aware of the cost of communication and data movement. Moreover, all communication operations are asynchronous by default, to enable programmers to write code that scales well even on hundreds of thousands of cores.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

Dynamically field-programmable qubit arrays (DPQA) have recently emerged as a promising platform for quantum information processing. In DPQA, atomic qubits are selectively loaded into arrays of optical traps that can be reconfigured during the computation itself. Leveraging qubit transport and parallel, entangling quantum operations, different pairs of qubits, even those initially far away, can be entangled at different stages of the quantum program execution. Such reconfigurability and non-local connectivity present new challenges for compilation, especially in the layout synthesis step which places and routes the qubits and schedules the gates. In this paper, we consider a DPQA architecture that contains multiple arrays and supports 2D array movements, representing cutting-edge experimental platforms. Within this architecture, we discretize the state space and formulate layout synthesis as a satisfiability modulo theories problem, which can be solved by existing solvers optimally in terms of circuit depth. For a set of benchmark circuits generated by random graphs with complex connectivities, our compiler OLSQ-DPQA reduces the number of two-qubit entangling gates on small problem instances by 1.7x compared to optimal compilation results on a fixed planar architecture. To further improve scalability and practicality of the method, we introduce a greedy heuristic inspired by the iterative peeling approach in classical integrated circuit routing. Using a hybrid approach that combined the greedy and optimal methods, we demonstrate that our DPQA-based compiled circuits feature reduced scaling overhead compared to a grid fixed architecture, resulting in 5.1X less two-qubit gates for 90 qubit quantum circuits. These methods enable programmable, complex quantum circuits with neutral atom quantum computers, as well as informing both future compilers and future hardware choices.

Physics↗

UPC++ v1.0 Programmer’s Guide, Revision 2020.3.0

UPC++ is a C++11 library that provides Partitioned Global Address Space (PGAS) programming. It is designed for writing parallel programs that run efficiently and scale well on distributed-memory parallel computers. The PGAS model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. However, PGAS also provides access to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ provides numerous methods for accessing and using global memory. In UPC++, all operations that access remote memory are explicit, which encourages programmers to be aware of the cost of communication and data movement. Moreover, all remote-memory access operations are by default asynchronous, to enable programmers to write code that scales well even on hundreds of thousands of cores.

97 MATHEMATICS AND COMPUTING↗

High Field Magnet Programme -- European Strategy Input

In this submission, we describe research goals, implementation, and timelines of the High Field Magnet Programme, hosted by CERN. The programme pursues accelerator-magnet R&D with low-temperature- and high-temperature superconductor technology with a main focus on the FCC-hh. Following a long tradition of magnet R&D for high-energy particle colliders, HFM R&D fosters important societal impact through synergies with other fields.

43 PARTICLE ACCELERATORS↗

A versatile pulse programmer for pulsed nuclear magnetic resonance spectroscopy.

A digital pulse programmer producing the standard pulse sequences required for pulsed nuclear magnetic resonance spectroscopy is described. In addition, a 'saturation burst' sequence, useful in the measurement of long relaxation times in solids, is provided. Both positive and negative 4 V trigger pulses are produced that are fully synchronous with a crystal-controlled time base, and the pulse programmer may be phase-locked with a maximum pulse jitter of 3 ns to the oscillator of a coherent pulse spectrometer. Medium speed TTL integrated circuits are used throughout.

Tarr, C. E.↗

Lunar observations verifier editor programmer's manual, revision 1

The prime purpose of the programmer's manual is to aid the programmer in understanding the programming aspects of the program. A description of the input, the printout, the deck setup, and tape configuration may be obtained from the LOVE user's guide.

Barnett, E. L.↗

A programmable sampling format telemetry system

This paper describes the programmable sampling format telemetry system to be used by the near-earth Small Astronomy Satellite-C (SAS-C) and possible future SAS missions. The concept of the programmable sampling format is introduced and the features of the system are illustrated by an example. The SAS-C telemetry system is described at the block diagram level and redundancy of the system is discussed briefly.

Peterson, M. R.↗

A programmable power processor for a 25 kW power module

The paper presents the concept and major design problems of a programmable power processor for the 25 kW electrical power system for the Shuttle Orbiter. The load will be handled by three parallel power stages operated in phase sequence with each power transistor having its own commutating diode and filter inductor. The power stages will be run at a fixed frequency of 10 kHz with the 'on'-time variable up to 100%. The input filter bank in the breadboard programmable power processor is planned to be a series-parallel combination of tantalum cased tantalum wet-slug capacitors.

Kapustka, R. E.↗

Programmable performance - One aspect of smart sensing systems

Programmable performance is the ability to flexibly alter basic spatial, spectral, and radiometric system response as a function of time. In this paper programmable performance is defined as a functional element of smart sensor systems for the 1990's. The uses and benefits of these classes of sensor systems are discussed with reference to multispectral scanners of the earth's surface. An overall technology trend is identified which couples a high degree of sensor performance flexibility to a need for advanced device technology developments.

Jobson, D. J.↗

An integrated control panel utilizing a programmable varistor-multiplexed dichroic liquid crystal display

Due to the conflicting demands of modern aircraft for increased systems/sensors and the decrease in cockpit panel size, weight, volume, and power, conventional discrete/dedicated methods of display and control are fast becoming obsolete. A means is sought to integrate the control and display into multifunctional programmable devices, thus giving the ability to increase system functions and yet conserve panel space. A potential solution to the control portion of the problem has come to be known as the Integrated Control Panel (ICP) approach. Flat panel display technology and controls using programmable flat panel displays with transparent capacitive touch control overlays offer the largest potential advantages. The flat panel display made of varistor-multiplexed dichroic liquid crystal (LCD) developed by GE in recent years appears to offer the ideal monochrome solution.

Whitton, I. J.↗

A fast, programmable hardware architecture for spaceborne SAR processing

The launch of spaceborne SARs during the 1980's is discussed. The satellite SARs require high quality and high throughput ground processors. Compression ratios in range and azimuth of greater than 500 and 150 respectively lead to frequency domain processing and data computation rates in excess of 2000 million real operations per second for C-band SARs under consideration. Various hardware architectures are examined and two promising candidates and proceeds to recommend a fast, programmable hardware architecture for spaceborne SAR processing are selected. Modularity and programmability are introduced as desirable attributes for the purpose of HTSP hardware selection.

Bennett, J. R.↗

A programmable power processor for high power space applications

A Programmable Power Processor (P3) has been developed for application in future large space power systems. The P3 is capable of operation over a wide range of input voltage (26 to 375 Vdc) and output voltage (24 to 180 Vdc). The peak output power capability is 18 kW (180 V at 100 A). The output characteristics of the P3 can be programmed to any voltage and/or current level within the limits of the processor and may be controlled as a function of internal or external parameters. Seven breadboard P3s and one 'flight-type' engineering model P3 have been built and tested both individually and in electrical power systems. The programmable feature allows the P3 to be used in a variety of applications by changing the output characteristics. Test results, including efficiency at various input/output combinations, transient response, and output impedance, are presented.

Lanier, J. R., Jr.↗