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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Loci-STREAM Version 0.9

Loci-STREAM is an evolving computational fluid dynamics (CFD) software tool for simulating possibly chemically reacting, possibly unsteady flows in diverse settings, including rocket engines, turbomachines, oil refineries, etc. Loci-STREAM implements a pressure- based flow-solving algorithm that utilizes unstructured grids. (The benefit of low memory usage by pressure-based algorithms is well recognized by experts in the field.) The algorithm is robust for flows at all speeds from zero to hypersonic. The flexibility of arbitrary polyhedral grids enables accurate, efficient simulation of flows in complex geometries, including those of plume-impingement problems. The present version - Loci-STREAM version 0.9 - includes an interface with the Portable, Extensible Toolkit for Scientific Computation (PETSc) library for access to enhanced linear-equation-solving programs therein that accelerate convergence toward a solution. The name "Loci" reflects the creation of this software within the Loci computational framework, which was developed at Mississippi State University for the primary purpose of simplifying the writing of complex multidisciplinary application programs to run in distributed-memory computing environments including clusters of personal computers. Loci has been designed to relieve application programmers of the details of programming for distributed-memory computers.

Wright, Jeffrey↗
NASA NTRS1980

Highly flexible pulse programmer for NMR applications

A pulse generator for NMR application is described. Eighteen output channels are provided to allow use in single and double resonance experiments. Complex pulse sequences may be generated by loading instructions into a 256-word by 16-bit program memory. Features of the pulse generator include programmable time delays from 0.5 micros to 1000 s, branching and looping instructions, and the ability to be loaded and operated either manually or from a PDP-11/10 computer.

Dart, J.↗
NASA NTRSDate not supplied

Parallelized Convolutional Interleaver Implementation for Efficient DDR Memory Access

Convolutional interleavers are used in many different communications systems to correct for burst errors due to atmospheric fades and scintillation. The interleaver size is related to the channel coherence time and the data rate. Small convolutional interleavers can be implemented in a field programmable gate array (FPGA) block random access memory (BRAM). However, large interleavers exceeding the size of the BRAM on the FPGA are necessary for channels with longer fades and higher data rates. Therefore, an implementation utilizing double data rate (DDR) memory external to the FPGA is necessary. Wide DDR memory data buses can make the use of DDR memory for convolutional interleavers inefficient when individual symbols are written to and read from the memory. DDR memory operational speeds can also limit the data rate of the interleaver. The Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency (HPE) standard utilizes a convolutional channel symbol interleaver. A previous implementation of the HPE standard utilized BRAM for the convolutional interleaver, but mission requirements for the upcoming Optical Artemis-2 Orion (O2O) communications demonstration dictate the use of an interleaver exceeding the size of the BRAM. An algorithm and method for implementing the convolutional interleaver in the FPGA with DDR memory is described in this paper.

optical communications↗
NASA NTRSDate not supplied

Parallelized convolutional interleaver implementation for efficient DDR memory access

Convolutional interleavers are used in many different communications systems to correct for burst errors due to atmospheric fades and scintillation. The interleaver size is related to the channel coherence time and the data rate. Small convolutional interleavers can be implemented in a field programmable gate array (FPGA) block random access memory (BRAM). However, large interleavers exceeding the size of the BRAM on the FPGA are necessary for channels with longer fades and higher data rates. Therefore, an implementation utilizing double data rate (DDR) memory external to the FPGA is necessary. Wide DDR memory data buses can make the use of DDR memory for convolutional interleavers inefficient when individual symbols are written to and read from the memory. DDR memory operational speeds can also limit the data rate of the interleaver. The Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency (HPE) standard utilizes a convolutional channel symbol interleaver. A previous implementation of the HPE standard utilized BRAM for the convolutional interleaver, but mission requirements for the upcoming Optical Artemis-2 Orion (O2O) communications demonstration dictate the use of an interleaver exceeding the size of the BRAM. An algorithm and method for implementing the convolutional interleaver in the FPGA with DDR memory is described in this paper.

Optical communications↗
NASA NTRS1971

Architectural design and simulation of a virtual memory

Virtual memory is an imaginary main memory with a very large capacity which the programmer has at his disposal. It greatly contributes to the solution of the dynamic storage allocation problem. The architectural design of a virtual memory is presented which implements by hardware the idea of queuing and scheduling the page requests to a paging drum in such a way that the access of the paging drum is increased many times. With the design, an increase of up to 16 times in page transfer rate is achievable when the virtual memory is heavily loaded. This in turn makes feasible a great increase in the system throughput.

Kwok, G.↗
NASA NTRS1975

Testability enhancement in digital system design

A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.

Chuang, C. S.↗
NASA NTRS1992

Real-time processor for the Danish airborne SAR

A real-time processor for the Danish high-resolution SAR is presented in terms of its functional performance, algorithm, architecture, and implementation. The real-time processor is mainly intended to assist the operator in using the SAR system, but since the processor has been designed to produce high-quality images, it is expected to make off-line processing superfluous in many cases. The range-Doppler algorithm is adopted and supplemented with an extensive motion compensation, considering the special conditions related to the real-time strip mapping of large scenes. The processor is a pipeline of about 20 elements interconnected by a dedicated data path and a control bus. Only three different types of elements are involved: a programmable signal processing element, a multipurpose memory element, and a multipurpose interface element. The prototypes of these three elements have been tested with satisfactory results.

Dall, J.↗
NASA NTRS2006

Radiation Tolerant Intelligent Memory Stack (RTIMS)

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Ng, Tak-kwong↗
NASA NTRS2011

Radiation-Tolerant Intelligent Memory Stack - RTIMS

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Ng, Tak-kwong↗
NASA NTRS1993

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗
NASA NTRS2024

Final Technical Report for CMSC 838L

This paper describes Rahul Vishnoi’s final project supporting in his Graduate School curriculum CMSC 838L, Advanced Topics in Programming Languages and Computer Architecture. This project was selected to intersect with his work as a Pathways Intern supporting Code 583, the Ground Software Systems Branch, at NASA’s Goddard Space Flight Center (GSFC). In this project, Field Programmable Gate Array (FPGA) hardware from Xilinx is used to replace and offload processor and memory-intensive computations from a microcontroller/Processing System (PS) to the FPGA Programmable Logic (PL). An interface between the PL and PS in the form of a C library allows for this bridging of capability.

Microcontroller, FPGA, Embedded Development, Xilin↗
NASA NTRS1992

A simple modern correctness condition for a space-based high-performance multiprocessor

A number of U.S. national programs, including space-based detection of ballistic missile launches, envisage putting significant computing power into space. Given sufficient progress in low-power VLSI, multichip-module packaging and liquid-cooling technologies, we will see design of high-performance multiprocessors for individual satellites. In very high speed implementations, performance depends critically on tolerating large latencies in interprocessor communication; without latency tolerance, performance is limited by the vastly differing time scales in processor and data-memory modules, including interconnect times. The modern approach to tolerating remote-communication cost in scalable, shared-memory multiprocessors is to use a multithreaded architecture, and alter the semantics of shared memory slightly, at the price of forcing the programmer either to reason about program correctness in a relaxed consistency model or to agree to program in a constrained style. The literature on multiprocessor correctness conditions has become increasingly complex, and sometimes confusing, which may hinder its practical application. We propose a simple modern correctness condition for a high-performance, shared-memory multiprocessor; the correctness condition is based on a simple interface between the multiprocessor architecture and a high-performance, shared-memory multiprocessor; the correctness condition is based on a simple interface between the multiprocessor architecture and the parallel programming system.

Probst, David K.↗
NASA NTRS1979

NASF transposition network: A computing network for unscrambling p-ordered vectors

The viewpoints of design, programming, and application of the transportation network (TN) is presented. The TN is a programmable combinational logic network that connects 521 memory modules to 512 processors. The unscrambling of p-ordered vectors to 1-ordered vectors in one cycle is described. The TN design is based upon the concept of cyclic groups from abstract algebra and primitive roots and indices from number theory. The programming of the TN is very simple, requiring only 20 bits: 10 bits for offset control and 10 bits for barrel switch shift control. This simple control is executed by the control unit (CU), not the processors. Any memory access by a processor must be coordinated with the CU and wait for all other processors to come to a synchronization point. These wait and synchronization events can be a degradation in performance to a computation. The TN application is for multidimensional data manipulation, matrix processing, and data sorting, and can also perform a perfect shuffle. Unlike other more complicated and powerful permutation networks, the TN cannot, if possible at all, unscramble non-p-ordered vectors in one cycle.

Lim, R. S.↗
NASA NTRS1997

A Comparison of PETSC Library and HPF Implementations of an Archetypal PDE Computation

Two paradigms for distributed-memory parallel computation that free the application programmer from the details of message passing are compared for an archetypal structured scientific computation a nonlinear, structured-grid partial differential equation boundary value problem using the same algorithm on the same hardware. Both paradigms, parallel libraries represented by Argonne's PETSC, and parallel languages represented by the Portland Group's HPF, are found to be easy to use for this problem class, and both are reasonably effective in exploiting concurrency after a short learning curve. The level of involvement required by the application programmer under either paradigm includes specification of the data partitioning (corresponding to a geometrically simple decomposition of the domain of the PDE). Programming in SPAM style for the PETSC library requires writing the routines that discretize the PDE and its Jacobian, managing subdomain-to-processor mappings (affine global- to-local index mappings), and interfacing to library solver routines. Programming for HPF requires a complete sequential implementation of the same algorithm, introducing concurrency through subdomain blocking (an effort similar to the index mapping), and modest experimentation with rewriting loops to elucidate to the compiler the latent concurrency. Correctness and scalability are cross-validated on up to 32 nodes of an IBM SP2.

Hayder, M. Ehtesham↗
NASA NTRS1999

Nano-Satellite Avionics

Abstract NASA's Goddard Space Flight Center (GSFC) is currently developing a new class of satellites called the nano-satellite (nano-sat). A major objective of this development effort is to provide the technology required to enable a constellation of tens to hundreds of nano-satellites to make both remote and in-situ measurements from space. The Nano-sat will be a spacecraft weighing a maximum of 10 kg, including the propellant mass, and producing at least 5 Watts of power to operate the spacecraft. The electronics are required to survive a total radiation dose rate of 100 krads for a mission lifetime of two years. There are many unique challenges that must be met in order to develop the avionics for such a spacecraft. The first challenge is to develop an architecture that will operate on the allotted 5 Watts and meet the diverging requirements of multiple missions. This architecture will need to incorporate a multitude of new advanced microelectronic technologies. The microelectronics developed must be a modular and scalable packaging of technology to solve the problem of developing a solution to both reduce cost and meet the requirements of various missions. This development will utilize the most cost effective approach, whether infusing commercially driven semiconductor devices into spacecraft applications or partnering with industry to design and develop low cost, low power, low mass, and high capacity data processing devices. This paper will discuss the nano-sat architecture and the major technologies that will be developed. The major technologies that will be covered include: (1) Light weight Low Power Electronics Packaging, (2) Radiation Hard/Tolerant, Low Power Processing Platforms, (3) High capacity Low Power Memory Systems (4) Radiation Hard reconfiguragble field programmable gate array (rFPGA)

Culver, Harry↗
NASA NTRS2007

High-Performance, Radiation-Hardened Electronics for Space Environments

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

Keys, Andrew S.↗
NASA NTRS1985

Man-machine interface and control of the shuttle digital flight system

The space shuttle main engine (SSME) presented new requirements in the design of controls for large pump fed liquid rocket engine systems. These requirements were the need for built in full mission support capability, and complexity and flexibility of function not previously needed in this type of application. An engine mounted programmable digital control system was developed to meet these requirements. The engine system and controller and their function are described. Design challenges encountered during the course of development included accommodation for a very severe engine environment, the implementation of redundancy and redundancy management to provide fail operational/fail safe capability, removal of heat from the package, and significant constraints on computer memory size and processing time. The flexibility offered by programmable control reshaped the approach to engine design and development and set the pattern for future controls development in these types of applications.

Burghduff, R. D.↗
NASA NTRS1998

Self-Calibrating and Remote Programmable Signal Conditioning Amplifier System and Method

A self-calibrating, remote programmable signal conditioning amplifier system employs information read from a memory attached to a measurement transducer for automatic calibration. The signal conditioning amplifier is self-calibrated on a continuous basis through use of a dual input path arrangement, with each path containing a multiplexer and a programmable amplifier. A digital signal processor controls operation of the system such that a transducer signal is applied to one of the input paths, while one or more calibration signals are applied to the second input path. Once the second path is calibrated, the digital signal processor switches the transducer signal to the second path. and then calibrates the first path. This process is continually repeated so that each path is calibrated on an essentially continuous basis. Dual output paths are also employed which are calibrated in the same manner. The digital signal processor also allows the implementation of a variety of digital filters which are either programmed into the system or downloaded by an operator, and performs up to eighth order linearization.

Medelius, Pedro J.↗