Results for “reconfigurable hardware” — Page 5

NASA NTRS2017

Immersive Simulations and Engineering Environment (iSEE)

In January 2017, the Immersive Simulations and Engineering Environment (iSEE), formally known as the Human Factor Tool (HFT), was brought back online. Since August, the lab had been operating at a nominal status, but with dated hardware. An evaluation was done on the present system so that the improvements and capabilities brought about by the upgrades can be quantified. Immediately following the analysis, evaluations with human factor engineers were performed and some upgrades were implemented. Due to a malfunction with a crucial piece of hardware, the lab was reconfigured temporarily. This allowed easy analysis and integration of various other components which improved the laboratories overall performance. Soon after, work began on creating a video to showcase the capabilities of the lab. This video not only served to show the actual functions of the lab, but also show the expanded capabilities the new hardware and software made available. Skills were acquired throughout the renovation process in various fields, all of which were crucial to not only implementing the updates to the lab, but understanding how they will improve it.

Motion Capture↗

NASA NTRS2004

EHW Approach to Temperature Compensation of Electronics

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

Stoica, Adrian↗

NASA NTRS1996

Neural Networks for Flight Control

Neural networks are being developed at NASA Ames Research Center to permit real-time adaptive control of time varying nonlinear systems, enhance the fault-tolerance of mission hardware, and permit online system reconfiguration. In general, the problem of controlling time varying nonlinear systems with unknown structures has not been solved. Adaptive neural control techniques show considerable promise and are being applied to technical challenges including automated docking of spacecraft, dynamic balancing of the space station centrifuge, online reconfiguration of damaged aircraft, and reducing cost of new air and spacecraft designs. Our experiences have shown that neural network algorithms solved certain problems that conventional control methods have been unable to effectively address. These include damage mitigation in nonlinear reconfiguration flight control, early performance estimation of new aircraft designs, compensation for damaged planetary mission hardware by using redundant manipulator capability, and space sensor platform stabilization. This presentation explored these developments in the context of neural network control theory. The discussion began with an overview of why neural control has proven attractive for NASA application domains. The more important issues in control system development were then discussed with references to significant technical advances in the literature. Examples of how these methods have been applied were given, followed by projections of emerging application needs and directions.

Jorgensen, Charles C.↗

NASA NTRS2016

Performance Analysis of a Hardware Implemented Complex Signal Kurtosis Radio-Frequency Interference Detector

Radio-frequency interference (RFI) is a known problem for passive remote sensing as evidenced in the L-band radiometers SMOS, Aquarius and more recently, SMAP. Various algorithms have been developed and implemented on SMAP to improve science measurements. This was achieved by the use of a digital microwave radiometer. RFI mitigation becomes more challenging for microwave radiometers operating at higher frequencies in shared allocations. At higher frequencies larger bandwidths are also desirable for lower measurement noise further adding to processing challenges. This work focuses on finding improved RFI mitigation techniques that will be effective at additional frequencies and at higher bandwidths. To aid the development and testing of applicable detection and mitigation techniques, a wide-band RFI algorithm testing environment has been developed using the Reconfigurable Open Architecture Computing Hardware System (ROACH) built by the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) Group. The testing environment also consists of various test equipment used to reproduce typical signals that a radiometer may see including those with and without RFI. The testing environment permits quick evaluations of RFI mitigation algorithms as well as show that they are implementable in hardware. The algorithm implemented is a complex signal kurtosis detector which was modeled and simulated. The complex signal kurtosis detector showed improved performance over the real kurtosis detector under certain conditions. The real kurtosis is implemented on SMAP at 24 MHz bandwidth. The complex signal kurtosis algorithm was then implemented in hardware at 200 MHz bandwidth using the ROACH. In this work, performance of the complex signal kurtosis and the real signal kurtosis are compared. Performance evaluations and comparisons in both simulation as well as experimental hardware implementations were done with the use of receiver operating characteristic (ROC) curves. The complex kurtosis algorithm has the potential to reduce data rate due to onboard processing in addition to improving RFI detection performance.

microwaves↗

NASA NTRS2016

Performance Analysis of a Hardware Implemented Complex Signal Kurtosis Radio-Frequency Interference Detector

Radio-frequency interference (RFI) is a known problem for passive remote sensing as evidenced in the L-band radiometers SMOS, Aquarius and more recently, SMAP. Various algorithms have been developed and implemented on SMAP to improve science measurements. This was achieved by the use of a digital microwave radiometer. RFI mitigation becomes more challenging for microwave radiometers operating at higher frequencies in shared allocations. At higher frequencies larger bandwidths are also desirable for lower measurement noise further adding to processing challenges. This work focuses on finding improved RFI mitigation techniques that will be effective at additional frequencies and at higher bandwidths. To aid the development and testing of applicable detection and mitigation techniques, a wide-band RFI algorithm testing environment has been developed using the Reconfigurable Open Architecture Computing Hardware System (ROACH) built by the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) Group. The testing environment also consists of various test equipment used to reproduce typical signals that a radiometer may see including those with and without RFI. The testing environment permits quick evaluations of RFI mitigation algorithms as well as show that they are implementable in hardware. The algorithm implemented is a complex signal kurtosis detector which was modeled and simulated. The complex signal kurtosis detector showed improved performance over the real kurtosis detector under certain conditions. The real kurtosis is implemented on SMAP at 24 MHz bandwidth. The complex signal kurtosis algorithm was then implemented in hardware at 200 MHz bandwidth using the ROACH. In this work, performance of the complex signal kurtosis and the real signal kurtosis are compared. Performance evaluations and comparisons in both simulation as well as experimental hardware implementations were done with the use of receiver operating characteristic (ROC) curves.

radiometers↗

NASA NTRS1996

Information Presentation and Control in a Modern Air Traffic Control Tower Simulator

The proper presentation and management of information in America's largest and busiest (Level V) air traffic control towers calls for an in-depth understanding of many different human-computer considerations: user interface design for graphical, radar, and text; manual and automated data input hardware; information/display output technology; reconfigurable workstations; workload assessment; and many other related subjects. This paper discusses these subjects in the context of the Surface Development and Test Facility (SDTF) currently under construction at NASA's Ames Research Center, a full scale, multi-manned, air traffic control simulator which will provide the "look and feel" of an actual airport tower cab. Special emphasis will be given to the human-computer interfaces required for the different kinds of information displayed at the various controller and supervisory positions and to the computer-aided design (CAD) and other analytic, computer-based tools used to develop the facility.

Haines, Richard F.↗

NASA NTRS2003

Hardware Evolution of Control Electronics

The evolution of closed-loop motor speed controllers implemented on the JPL FPTA2 is presented. The response of evolved controller to sinusoidal commands, controller reconfiguration for fault tolerance,and hardware evolution are described.

Gwaltney, David↗

NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗

NASA NTRS1999

Design Description of the X-33 Avionics Architecture

In this paper, we provide a design description of the X-33 avionics architecture. The X-33 is an autonomous Single Stage to Orbit (SSTO) launch vehicle currently being developed by Lockheed Martin for NASA as a technology demonstrator for the VentureStar Reusable Launch Vehicle (RLV). The X-33 avionics provides autonomous control of die vehicle throughout takeoff, ascent, descent, approach, landing, rollout, and vehicle safing. During flight the avionics provides communication to the range through uplinked commands and downlinked telemetry. During pre-launch and post-safing activities, the avionics provides interfaces to ground support consoles that perform vehicle flight preparations and maintenance. The X-33 Avionics is a hybrid of centralized and distributed processing elements connected by three dual redundant Mil-Std 1553 data buses. These data buses are controlled by a central processing suite located in the avionics bay and composed of triplex redundant Vehicle Mission Computers (VMCs). The VMCs integrate mission management, guidance, navigation, flight control, subsystem control and redundancy management functions. The vehicle sensors, effectors and subsystems are interfaced directly to the centralized VMCs as remote terminals or through dual redundant Data Interface Units (DIUs). The DIUs are located forward and aft of the avionics bay and provide signal conditioning, health monitoring, low level subsystem control and data interface functions. Each VMC is connected to all three redundant 1553 data buses for monitoring and provides a complete identical data set to the processing algorithms. This enables bus faults to be detected and reconfigured through a voted bus control configuration. Data is also shared between VMCs though a cross channel data link that is implemented in hardware and controlled by AlliedSignal's Fault Tolerant Executive (FTE). The FTE synchronizes processors within the VMC and synchronizes redundant VMCs to each other. The FTE provides an output-voting plane to detect, isolate and contain faults due to internal hardware or software faults and reconfigures the VMCs to accommodate these faults. Critical data in the 1553 messages are scheduled and synchronized to specific processing frames in order to minimize data latency. In order to achieve an open architecture, military and commercial off-the-shelf equipment is incorporated using common processors, standard VME backplanes and chassis, the VxWorks operating system, and MartixX for automatic code generation. The use of off-the-shelf tools and equipment helps reduce development time and enables software reuse. The open architecture allows for technology insertion, while the distributed modular elements allow for expansion to increased redundancy levels to meet the higher reliability goals of future RLVs.

Reichenfeld, Curtis J.↗

NASA NTRS2008

STRS Compliant FPGA Waveform Development

The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. A FPGA-based transmit waveform implementation of the proposed standard interfaces on a laboratory breadboard SDR will be discussed.

Nappier, Jennifer↗

NASA NTRS2017

Reconfiguration of NASA GRC's Vacuum Facility 6 for Testing of Advanced Electric Propulsion System (AEPS) Hardware

The NASA Hall Effect Rocket with Magnetic Shielding (HERMeS) 12.5 kilowatt Hall thruster has been the subject of extensive technology maturation in preparation for development into a flight propulsion system. The HERMeS thruster is being developed and tested at NASA GRC and NASA JPL through support of the Space Technology Mission Directorate and is intended to be used as the electric propulsion system on the Power and Propulsion Element of the recently announced Deep Space Gateway. The Advanced Electric Propulsion System (AEPS) contract was awarded to Aerojet Rocketdyne to develop the HERMeS system into a flight system for use by NASA. To address the hardware test needs of the AEPS project, NASA GRC launched an effort to reconfigure Vacuum Facility 6 for high-power electric propulsion testing including upgrades and reconfigurations necessary to conduct performance, plasma plume, and system level integration testing. Results of the verification and validation testing with HERMeS Technology Demonstration Unit (TDU) 1 and TDU-3 Hall thrusters are also included.

ion engines↗

NASA NTRS2016

Reconfiguration of NASA GRC's Vacuum Facility 6 for Testing of Advanced Electric Propulsion System (AEPS) Hardware

The NASA Hall Effect Rocket with Magnetic Shielding (HERMeS) 12.5 kilowatt Hall thruster has been the subject of extensive technology maturation in preparation for development into a flight propulsion system. The HERMeS thruster is being developed and tested at NASA GRC and NASA JPL through support of the Space Technology Mission Directorate and is intended to be used as the electric propulsion system on the Power and Propulsion Element of the recently announced Deep Space Gateway. The Advanced Electric Propulsion System (AEPS) contract was awarded to Aerojet Rocketdyne to develop the HERMeS system into a flight system for use by NASA. To address the hardware test needs of the AEPS project, NASA GRC launched an effort to reconfigure Vacuum Facility 6 for high-power electric propulsion testing including upgrades and reconfigurations necessary to conduct performance, plasma plume, and system level integration testing. Results of the verification and validation testing with HERMeS Technology Demonstration Unit (TDU) 1 and TDU-3 Hall thrusters are also included.

life (durability)↗

NASA NTRS2018

Reconfiguration of NASA GRC's Vacuum Facility 6 for Testing of Advanced Electric Propulsion System (AEPS) Hardware

The NASA Hall Effect Rocket with Magnetic Shielding (HERMeS) 12.5 kW Hall thruster has been the subject of extensive technology maturation in preparation for development into a flight propulsion system. The HERMeS thruster is being developed and tested at NASA GRC and NASA JPL through support of the Space Technology Mission Directorate (STMD) and is intended to be used as the electric propulsion system on the Power and Propulsion Element (PPE) of the recently announced Deep Space Gateway (DSG). The Advanced Electric Propulsion System (AEPS) contract was awarded to Aerojet-Rocketdyne to develop the HERMeS system into a flight system for use by NASA. To address the hardware test needs of the AEPS project, NASA GRC launched an effort to reconfigure Vacuum Facility 6 (VF-6) for high-power electric propulsion testing including upgrades and reconfigurations necessary to conduct performance, plasma plume, and system level integration testing. Results of the verification and validation testing with HERMeS Technology Demonstration Unit (TDU)-1 and TDU-3 Hall thrusters are also included.

Peterson, Peter Y.↗

NASA NTRS2004

Evolutionary recovery from radiation induced faults and reconfigurable devices

Radiation hardening technologies for electronics are the conventional approach for survivability in high radiation environments. This paper presents a novel approach based on evolvable hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged compoenents.

Daud, Taher↗

NASA NTRS2006

Evaluation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Array

The current implementation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays (TRIGA) is equipped with CFDP protocol and CCSDS Telemetry and Telecommand framing schemes to replace the CPU intensive software counterpart implementation for reliable deep space communication. We present the hardware/software co-design methodology used to accomplish high data rate throughput. The hardware CFDP protocol stack implementation is then compared against the two recent flight implementations. The results from our experiments show that TRIGA offers more than 3 orders of magnitude throughput improvement with less than one-tenth of the power consumption.

protocol processing hardware↗

NASA NTRS2011

Component-Level Electronic-Assembly Repair (CLEAR) System Architecture

This document captures the system architecture for a Component-Level Electronic-Assembly Repair (CLEAR) capability needed for electronics maintenance and repair of the Constellation Program (CxP). CLEAR is intended to improve flight system supportability and reduce the mass of spares required to maintain the electronics of human rated spacecraft on long duration missions. By necessity it allows the crew to make repairs that would otherwise be performed by Earth based repair depots. Because of practical knowledge and skill limitations of small spaceflight crews they must be augmented by Earth based support crews and automated repair equipment. This system architecture covers the complete system from ground-user to flight hardware and flight crew and defines an Earth segment and a Space segment. The Earth Segment involves database management, operational planning, and remote equipment programming and validation processes. The Space Segment involves the automated diagnostic, test and repair equipment required for a complete repair process. This document defines three major subsystems including, tele-operations that links the flight hardware to ground support, highly reconfigurable diagnostics and test instruments, and a CLEAR Repair Apparatus that automates the physical repair process.

Oeftering, Richard C.↗

NASA NTRS2019

Further Development Of Aperture: A Precise Extremely Large Reflective Telescope Using Re-Configurable Elements: NASA Innovative Advanced Concepts (NIAC) - Phase II

One of the pressing needs for space ultraviolet-visible astronomy is a design to allow larger mirrors than the James Webb Space Telescope primary. The diameter of the rocket fairing limits the mirror diameter such that all future missions calling for mirrors up to 16 meters in diameter or larger will require a mirror that is deployed post-launch. In response to the deployment requirement, we address the issues of this concept called "A Precise Extremely Large Reflective Telescope Using Reconfigurable Elements (APERTURE) with both hardware experiments and software simulations... We designed and built several fixtures with O-rings to hold a membrane. We established a coating process to make a membrane that was coated on one side with Cr and the other side with Cr-Terfenol-D-NiCo. The Terfenol-D (T-D hereafter) is the MSM (Magnetic Smart Memory) we use. We bought and established a procedure for measuring a deformation over time and purchased a Shack Hartmann system from Imagine Optic (https://www.imagine-optic.com). The first substrate we used was DuPont (TM) Kapton® polyimide film. Due to material creep, we found the stability over a 48-hour period with a Kapton substrate was not as good as desired (greater than 1 micron). We then switched to CP1 Polyimide. We found the CP1 much more stable to creep, being stable from about 3 hours to 48 hours to within a measurement error to below approximately 0.1 micron. We produced a 13 micron maximum deviation on a 50-millimeter-diameter piece of CP1 (25 microns thick). The T-D coating was about 2 microns, and the other layers, about 10 nanometers. The magnetic field at the base was about 0.1 teslas. We can make the T-D film at least 5 times thicker and the magnetic field at least 5 times stronger, and hence make deformations as much as 25 times larger. We have a formed a collaboration produced at the NIAC (NASA Innovative Advanced Concepts) mid-term review with Dr. Ron Shiri of Goddard Space Flight Center (GSFC) to explore making controlled deviations on lambda/14-lambda/20 scales which are required to bring a surface to the diffraction limit. We carried out only preliminary work on Si using a Coordinate Measuring Machine (CMM), which produced deviations on the 1 micron level. We are still working on a program to bring to GSFC a flat enough (radius of curvature greater than 10 microns) -coated a Si piece with Cr, T-D, NiCo. Then we plan to carry out tests with an interferometer. Further, we formed a new collaboration with Prof. Rajan Vaidyanathan of the University of Central Florida to replace the CP1 with a shape memory alloy (SMA). With his collaboration, we acquired new Federal funding outside of NASA to explore the use of SMAs (we use NiTi). Our preliminary results indicate that we can produce deformations greater than 1 micron on approximately 100 microns thick. Furthermore we have shown that the NiTi can deploy to better than 1 micron of its set original and then trained shape.

Re-Configurable Elements↗

NASA NTRS2005

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

evolvable hardware↗