Overview of non-volatile testing and screening methods
This paper outlines several testing issues posed by novel memories and approaches to testing for radiation and reliability effects.
non-volatile↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite
NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.
MacLeod, Todd C.↗
Learning efficient erasure protocols for an underdamped memory
Here we apply evolutionary reinforcement learning to a simulation model to identify efficient time-dependent erasure protocols for a physical realization of a 1-bit memory using an underdamped mechanical cantilever. We show that these protocols, when applied to the cantilever in the laboratory, are considerably more efficient than our best hand-designed protocols. The learned protocols allow reliable high-speed erasure by minimizing the heating of the memory during its operation. More generally, the combination of methods used here opens the door to the rational design of efficient protocols for various physics applications.
74 ATOMIC AND MOLECULAR PHYSICS↗
Error control for reliable digital data transmission and storage systems
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code.
Costello, D. J., Jr.↗
Compact Spare-Row Decoder For Computer Memory
Spare-row memory-address-decoder circuit commanded to address ninth row in computer memory instead of addressing one of eight others it would address normally. Variants used to construct small, highly reliable computers. Spare-row decoder offers advantages of compactness, efficiency, and performance. Requires only 12.5 percent memory overhead. System equipped with spare-row decoder requires less glue logic and exhibits greater through-put. Applications include computers in Hitchhiker Central Unit embedded computer on Cassini spacecraft. Concept of circuit applicable to most flight computer systems.
Katz, Richard B.↗
Test-retest reliability of cognitive EEG
OBJECTIVE: Task-related EEG is sensitive to changes in cognitive state produced by increased task difficulty and by transient impairment. If task-related EEG has high test-retest reliability, it could be used as part of a clinical test to assess changes in cognitive function. The aim of this study was to determine the reliability of the EEG recorded during the performance of a working memory (WM) task and a psychomotor vigilance task (PVT). METHODS: EEG was recorded while subjects rested quietly and while they performed the tasks. Within session (test-retest interval of approximately 1 h) and between session (test-retest interval of approximately 7 days) reliability was calculated for four EEG components: frontal midline theta at Fz, posterior theta at Pz, and slow and fast alpha at Pz. RESULTS: Task-related EEG was highly reliable within and between sessions (r0.9 for all components in WM task, and r0.8 for all components in the PVT). Resting EEG also showed high reliability, although the magnitude of the correlation was somewhat smaller than that of the task-related EEG (r0.7 for all 4 components). CONCLUSIONS: These results suggest that under appropriate conditions, task-related EEG has sufficient retest reliability for use in assessing clinical changes in cognitive status.
Non-NASA Center↗
Camera memory study for large space telescope
Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.
Hoffman, C. P.↗
System applications of the fault tolerant memory
Conventional memory technologies currently employed in aerospace applications contribute at least fifty percent to system unreliability (where the system includes CPU, I/O and memory). A fault tolerant memory performs both error correction and memory replacement at the bit plane level. To determine the effects of system design of using a fault tolerant memory in space applications, analysis was performed to determine tradeable hardware configurations that meet the reliability goals of each program. The candidate configurations, which included redundant elements of the computer system with both conventional and fault tolerant memories, were then traded in terms of selection criteria of cost, weight, volume, and power. These trade studies demonstrated that a fault tolerant memory provided significant advantages in terms of cost, weight, and volume. The memory selected for this analysis was a recently developed five fault tolerant memory.
Murphy, L. J.↗
Disturb testing in flash memories
Non-volatile memory technology as defined by NAND architecture flash memory continues to lead the process scaling and device shrinking efforts of the entire integrated circuit industry. 45- nm technology nodes are now producing commercial 32Gb devices. These latest 32Gb devices are pioneering new charge trapping memory cell technologies using metal gates and high-k dielectric materials. These cells are called TANOS and consist of tantalum-nitride, aluminum oxide (high k material), nitride, oxide, and silicon. Such high-density memories continue to revolutionize commercial electronics in terms of new high-speed data architectures and significant reductions in overall power and weight consumption. In stark contrast, nearly all science-based interplanetary and earth-orbiting NASA spacecraft are still designing in and around mid-1980s-level non-volatile technology with 1Mb Electrically Erasable Read-Only Memory (EEPROM) devices. NASA has typically shunned the use of modern flash devices because of radiation and reliability concerns due to the commercial-offthe– shelf (COTS) nature of the NAND flash technology. Given the significant potential increases in overall system capability these modern flash devices could bring to NASA missions, it is important to continue to investigate these devices. This report will investigate certain portions of the reliability performance of NAND flash devices, specifically the disturb properties. Understanding the possible limitations such new non-volatile memory technology presents to NASA is the goal of this report.
Freie, Michael↗
New double-byte error-correcting codes for memory systems
Error-correcting or error-detecting codes have been used in the computer industry to increase reliability, reduce service costs, and maintain data integrity. The single-byte error-correcting and double-byte error-detecting (SbEC-DbED) codes have been successfully used in computer memory subsystems. There are many methods to construct double-byte error-correcting (DBEC) codes. In the present paper we construct a class of double-byte error-correcting codes, which are more efficient than those known to be optimum, and a decoding procedure for our codes is also considered.
Feng, Gui-Liang↗
Applications of cold hibernated elastic memory (CHEM) structures
Experiments and analyses have confirmed the feasibility of an innovative, new class of very simple, reliable, low mass, low packaging volume, and low-cost self-deployable structures for space and commercial applications.
shape memory polymers open cellular structures exp↗
ALD-Derived WO 3– x Leads to Nearly Wake-Up-Free Ferroelectric Hf 0.5 Zr 0.5 O 2 at Elevated Temperatures
Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics─either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures, such as 125°C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO 2 -based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO 3–x ) layer─known as an oxygen reservoir─and carefully tuning its oxygen content, ultrathin Hf 0.5 Zr 0.5 O 2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 10 5 to only 10 at 125°C, a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory (DFT) calculations reveal that WO 3 enhances the stability of the ferroelectric orthorhombic phase (o-phase) at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.
36 MATERIALS SCIENCE↗
VA EDH Advanced Software Pipeline Framework Report: Enhancing Automation and Scalability
The VA Environmental Determinants of Health (EDH) Advanced Software Pipeline Framework is designed to enhance the efficiency, scalability, and security of geospatial data processing workflows. This framework integrates modern data orchestration and containerization technologies, including Prefect for workflow automation, Docker for containerization, and PostgreSQL/PostGIS for geospatial data storage and analysis. It ensures standardized, reproducible, and automated data processing, supporting VA objectives related to substance use risk assessment and recovery research. The pipeline addresses key scalability and performance challenges through horizontal and vertical scaling, high-performance computing (HPC) integration, parallel processing, task caching, and dynamic resource allocation. These optimizations improve throughput and reduce latency, allowing the system to efficiently manage large and complex datasets. Additionally, security and compliance measures—such as data encryption (SSL), Role-Based Access Control (RBAC), and adherence to GDPR and HIPAA standards—safeguard sensitive information throughout data transmission and storage. A key implementation of this framework includes the automation of shelter list geolocation workflows, ensuring that up-to-date data is readily available for VA decision-making. Lessons learned from this project include the transition from in-memory processing to incremental storage writes, improving resource management and reliability. Future enhancements aim to expand automation, integrate AI-driven anomaly detection, and incorporate high-performance computing resources. This framework provides a scalable, secure, and adaptable solution for managing geospatial datasets, reinforcing the VA’s ability to support clinical and strategic initiatives through data-driven decision-making.
97 MATHEMATICS AND COMPUTING↗
Cold Hibernated Elastic Memory (CHEM) Self-Deployable Structures
Experiments have confirmed the feasibility of an innovative, new class of very simple, reliable, low mass, low packaging volume, and low-cost self-deployable structures for space and commercial applications.
Cold↗
Precipitation Strengthenable NiTiPd High Temperature Shape Memory Alloys
In binary NiTi alloys, it has long been known that Ni-rich alloys can be heat treated to produce precipitates which both strengthen the matrix against dislocations and improve the behavior of the material under thermal and mechanical cycling. Within recent years, the same effect has been observed in Ni-rich NiTiHf high temperature shape memory alloys and heat treatment regimens have been defined which will reliably produce improved properties. In NiTiPd alloys, precipitation has also been observed, but studies are still underway to define reliable heat treatments and compositions which will provide a balance of strengthening and good thermomechanical properties. For this study, a series of NiTi-32 at.Pd alloys was produced to determine the effect of changing nickeltitanium content on the transformation behavior and heat treatability of the material. Samples were aged at temperatures between 350C and 450C for times up to 100 hours. Actuation type behavior was evaluated using uniaxial constant force thermal cycling (UCFTC) to determine the effect of composition and aging on the material behavior. TEMSEM was used to evaluate the microstructure and determine the types of precipitates formed. The correlation between composition, heat treat, microstructure, and thermomechanical behavior will be addressed and discussed.
Transformation strain↗
Reliability Characterization of TaOx-Based Commercial ReRAM in Combination with Radiation
We present reliability data combined with total dose gamma radiation for one of the first commercially available resistive memory devices. These Tantalum Oxide (TaOX)-based resistive memory chips demonstrate operation in dynamic program and erase testing up to ~130 Krad(Si) of 60Co gamma dose. In static and unbiased conditions, the stored data in the memory cells were able to withstand up to 50Mrad(Si) of exposure. The access circuitry, though, seemed less robust to gamma radiation and was able to operate only up to a total dose of 3Mrad(Si). Post exposure reliability as indicated by endurance, cycling error rate, and data retention tests showed no detectable impact from the combination with prior gamma irradiation. Overall, the total dose radiation tolerance of the commercial TaOx-based resistive memory chip appears to be higher than flash memory chips and in agreement with prior tests conducted with single cell resistive memories.
total ionizing dose↗
Multipulse current source offers low power losses and high reliability
Pulse current source uses low loss, high reliability, LC circuits to provide the necessary high impedance for magnetic memory cores, frequently used in digital computational equipment. Square-loop reactors replace the semiconductor switches previously used.
Source record↗
A portable battery for objective, non-obstrusive measures of human performances
The need for a standardized battery of human performance tests to measure the effects of various treatments is pointed out. Progress in such a program is reported. Three batteries are available which differ in length and the number of tests in the battery. All tests are implemented on a portable, lap held, briefcase size microprocessor. Performances measured include: information processing, memory, visual perception, reasoning, and motor skills, programs to determine norms, reliabilities, stabilities, factor structure of tests, comparisons with marker tests, apparatus suitability. Rationale for the battery is provided.
Kennedy, R. S.↗