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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Integrated infrared array technology

An overview of integrated infrared (IR) array technology is presented. Although the array pixel formats are smaller, and the readout noise of IR arrays is larger than the corresponding values achieved with optical charge-coupled-device silicon technology, substantial progress is being made in IR technology. Both existing IR arrays and those being developed are described. Examples of astronomical images are given which illustrate the potential of integrated IR arrays for scientific investigations.

Goebel, J. H.↗
NASA NTRS1989

Nuclear fragmentation studies for microelectronic application

A formalism for target fragment transport is presented with application to energy loss spectra in thin silicon devices. Predicted results are compared to experiments with the surface barrier detectors of McNulty et al. The intranuclear cascade nuclear reaction model does not predict the McNulty experimental data for the highest energy events. A semiempirical nuclear cross section gives an adequate explanation of McNulty's experiments. Application of the formalism to specific electronic devices is discussed.

Ngo, Duc M.↗
NASA NTRS1989

Parallel asynchronous systems and image processing algorithms

A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.

Coon, D. D.↗
NASA NTRS1991

Theoretical prediction of the impact of Auger recombination on charge collection from an ion track

A recombination mechanism that significantly reduces charge collection from very dense ion tracks in silicon devices was postulated by Zoutendyk et al. The theoretical analysis presented here concludes that Auger recombination is such a mechanism and is of marginal importance for higher density tracks produced by 270-MeV krypton, but of major importance for higher density tracks. The analysis shows that recombination loss is profoundly affected by track diffusion. As the track diffuses, the density and recombination rate decrease so fast that the linear density (number of electron-hole pairs per unit length) approaches a non-zero limiting value as t yields infinity. Furthermore, the linear density is very nearly equal to this limiting value in a few picoseconds or less. When Auger recombination accompanies charge transport processes that have much longer time scales, it can be simulated by assigning a reduced linear energy transfer to the ion.

Edmonds, Larry D.↗
NASA NTRS1991

Theoretical prediction of the impact of Auger recombination on charge collection from an ion track

The theoretical analysis presented indicates that Auger recombination can reduce charge collection from very dense ion tracks in silicon devices. It is of marginal importance for tracks produced by 270-MeV krypton, and therefore it is of major importance for ions exhibiting a significantly larger loss. The analysis shows that recombination loss is profoundly affected by track diffusion. As the track diffuses, the density and recombination rate decrease so fast that the linear density (number of electron-hole pairs per unit length) approaches a nonzero limiting value as t approaches infinity. Furthermore, the linear density is very nearly equal to this limiting value in a few picoseconds or less. When Auger recombination accompanies charge transport processes that have much longer time scales, it can be simulated by assigning a reduced linear energy transfer to the ion.

Edmonds, Larry D.↗
NASA NTRS1992

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Fossum, Eric R.↗
NASA NTRS2009

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Patterson, Richard↗
NASA NTRS2012

Use of Functionalized Carbon Nanotubes for Covalent Attachment of Nanotubes to Silicon

The purpose of the invention is to covalently attach functionalized carbon nanotubes to silicon. This step allows for the introduction of carbon nanotubes onto all manner of silicon surfaces, and thereby introduction of carbon nano - tubes covalently into silicon-based devices, onto silicon particles, and onto silicon surfaces. Single-walled carbon nanotubes (SWNTs) dispersed as individuals in surfactant were functionalized. The nano - tube was first treated with 4-t-butylbenzenediazonium tetrafluoroborate to give increased solubility to the carbon nanotube; the second group attached to the sidewall of the nanotube has a silyl-protected terminal alkyne that is de-protected in situ. This gives a soluble carbon nanotube that has functional groups appended to the sidewall that can be attached covalently to silicon. This reaction was monitored by UV/vis/NJR to assure direct covalent functionalization.

Tour, James M.↗
NASA NTRS2014

Toward Large-Area Sub-Arcsecond X-Ray Telescopes

The future of x-ray astronomy depends upon development of x-ray telescopes with larger aperture areas (>1 sq m) and finer angular resolution(<1).Combined with the special requirements of nested grazing incidence optics, the mass and envelope constraints of spaceborne telescopes render such advances technologically challenging. Achieving this goal will require precision fabrication, alignment, mounting, and assembly of large areas (>100 sq m) of lightweight (1 kg/sq m areal density) high quality mirrors-possibly entailing active (in-space adjustable) alignment and figure correction. This paper discusses relevant programmatic and technological issues and summarizes progress toward large area sub-arcsecond x-ray telescopes. Key words: X-ray telescopes, x-ray optics, active optics, electroactive devices, silicon mirrors, differential deposition, ion implantation.

O'Dell, Stephen L.↗
NASA NTRS1979

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Chapman, P. W.↗
NASA NTRS1979

Silicon-on-ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

Significant progress is reported in fabricating a 4 sq cm cell having a 10.1 percent conversion efficiency and a 10 sq cm cell having a 9.2 percent conversion efficiency. The continuous (SCIM) coater succeeded in producing a 16 sq cm coating exhibiting unidirectional solidification and large grain size. A layer was grown at 0.2 cm/sec in the experimental coater which was partially dendritic but also contained a large smooth area approximately 100 micron m thick. The dark characteristic measurements of a typical SCC solar cell yield shunt resistance values of 10K ohms and series resistance values and 0.4 ohm. The production dip-coater is operating at over 50 percent yield in terms of good cell quality material. The most recent run yielded 13 good substrates out of 15.

Chapman, P. W.↗
NASA NTRS1979

Silicon-on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

The technical and economic feasibility of producing solar cell-quality silicon was investigated. This was done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress in the following areas was demonstrated: (1) fabricating a 10 sq cm cell having 9.9 percent conversion efficiency; (2) producing a 225 sq cm layer of sheet silicon; and (3) obtaining 100 microns thick coatings at pull speed of 0.15 cm/sec, although approximately 50 percent of the layer exhibited dendritic growth.

Chapman, P. W.↗
NASA NTRS1981

Silicon-on-ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

The technical feasibility of producing solar cell quality sheet silicon to meet the DOE 1986 cost goal of 70 cents/watt was investigated. The silicon on ceramic approach is to coat a low cost ceramic substrate with large grain polycrystalline silicon by unidirectional solidification of molten silicon. Results and accomplishments are summarized.

Whitehead, A. B.↗
NASA NTRS1981

Silicon-on ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

The technical feasibility of producing solar-cell-quality sheet silicon to meet the Department of Energy (DOE) 1986 overall price goal of $0.70/watt was investigated. With the silicon-on-ceramic (SOC) approach, a low-cost ceramic substrate is coated with large-grain polycrystalline silicon by unidirectional solidification of molten silicon. This effort was divided into several areas of investigation in order to most efficiently meet the goals of the program. These areas include: (1) dip-coating; (2) continuous coating designated SCIM-coating, and acronym for Silicon Coating by an Inverted Meniscus (SCIM); (3) material characterization; (4) cell fabrication and evaluation; and (5) theoretical analysis. Both coating approaches were successful in producing thin layers of large grain, solar-cell-quality silicon. The dip-coating approach was initially investigated and considerable effort was given to this technique. The SCIM technique was adopted because of its scale-up potential and its capability to produce more conventiently large areas of SOC.

Grung, B. L.↗
NASA NTRS1998

Preparation and Surface Analysis of a Fluorinated Amorphous Silicon for Photo-voltaic Device Application

Amorphous silicon films (a-Si:H) have been routinely deposited on a variety of substrates. Surface and interfacial studies were carried out with a PHI 5600 X-ray photo electron spectrometer. Co-deposition with fluorine yielded films having oxygen present as bulk oxide. The higher the fluorine content, the greater the amount of bulk oxygen observed. The presence of oxygen may be a contributing factor to inconsistent film properties of fluorine doped silicon materials, reported else where. A definite chemical interface between a layer containing fluorine and a layer made from pure silane has been delineated.

McWhinney, Hylton G.↗
NASA NTRS1991

Development of silicon carbide semiconductor devices for high temperature applications

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Matus, Lawrence G.↗