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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5

An integrated eddy current detection and imaging system on a silicon chip

Eddy current probes have been used for many years for numerous sensing applications including crack detection in metals. However, these applications have traditionally used the eddy current effect in the form of a physically wound single or different probe pairs which of necessity must be made quite large compared to microelectronics dimensions. Also, the traditional wound probe can only take a point reading, although that point might include tens of individual cracks or crack arrays; thus, conventional eddy current probes are beset by two major problems: (1) no detailed information can be obtained about the crack or crack array; and (2) for applications such as quality assurance, a vast amount of time must be taken to scan a complete surface. Laboratory efforts have been made to fabricate linear arrays of single turn probes in a thick film format on a ceramic substrate as well as in a flexible cable format; however, such efforts inherently suffer from relatively large size requirements as well as sensitivity issues. Preliminary efforts to fully extend eddy current probing from a point or single dimensional level to a two dimensional micro-eddy current format on a silicon chip, which might overcome all of the above problems, are presented.

Henderson, H. Thurman↗

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗

Wireless Capacitive Pressure Sensor With Directional RF Chip Antenna for High Temperature Environments

This paper presents the design, fabrication and characterization of a wireless capacitive pressure sensor with directional RF chip antenna that is envisioned for the health monitoring of aircraft engines operating in harsh environments. The sensing system is characterized from room temperature (25 C) to 300 C for a pressure range from 0 to 100 psi. The wireless pressure system consists of a Clapp-type oscillator design with a capacitive MEMS pressure sensor located in the LC-tank circuit of the oscillator. Therefore, as the pressure of the aircraft engine changes, so does the output resonant frequency of the sensing system. A chip antenna is integrated to transmit the system output to a receive antenna 10 m away.The design frequency of the wireless pressure sensor is 127 MHz and a 2 increase in resonant frequency over the temperature range of 25 to 300 C from 0 to 100 psi is observed. The phase noise is less than minus 30 dBcHz at the 1 kHz offset and decreases to less than minus 80 dBcHz at 10 kHz over the entire temperature range. The RF radiation patterns for two cuts of the wireless system have been measured and show that the system is highly directional and the MEMS pressure sensor is extremely linear from 0 to 100 psi.

Pressure sensor↗

Proton Testing of nVidia Jetson TX2

Single-Event Effects (SEE) testing was conducted on the nVidia Jetson TX2 System on Chip (SOC). Testing was conducted at Massachusetts General Hospital's (MGH) Francis H. Burr Proton Therapy Center on June 2nd, 2019.

System on Chip (SOC)↗

An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

Deutsch, L. J.↗

Low volume packaging for a microinstrumentation system

A folding, multi-platform assembly has been developed for the packaging of a multi-chip microinstrumentation system. The assembly includes three solid platforms connected by flexible micromachined ribbon cables and it can be populated by sensors and electronics from a variety of technologies including surface mount and integrated circuit (IC) processes. The entire structure is fabricated from a four-inch silicon wafer using a simple four mask process and a post-process EDP etch. The micromachined ribbon cables allow the platform assembly to be folded into a three level structure with control electronics on the bottom level, microsensors and interface electronics on the second level, and sensors that need environmental access on the top level. Using the silicon multi-platform assembly, a prototype microinstrumentation system has been developed that includes a microcontroller unit and sensors for measuring temperature, barometric pressure, humidity, altitude, and acceleration as well as a telemetry device for wireless communication. When folded in the three level structure, this microsystem occupies only 5 cc and can be placed in an outer case the size of a wristwatch.

Mason, A.↗

Thermal Systems Modeling of Chemical Integrated Power Source (CHIPS) to Survive Lunar Night Environments

This paper presents the results of the systems level thermal modeling for a conceptual Chemical Heat Integrated Power Source (CHIPS). This proposed system offers a combined thermal and electrical power source to support survival of spacecraft operating in extreme low temperature lunar environments, without the use of radioisotope-based sources. A conceptual design study has been completed for this system, that uses heat generated by an exothermic chemical reaction in place of radioisotope or electrical heat sources. The goal of the study was to evaluate the feasibility of such as system through thermodynamic and chemical analysis and thermal modeling, and to identify technology gaps to inform a technology development and maturation plan. The specific technical objectives focused on delivery of 90-100 Wth thermal power and 30-40 We electrical power for 336 hours to a representative Commercial Lunar Payload Services (CLPS) lander, to support lunar surface survival and limited operations through a lunar night. The total system mass was targeted at ≤50 kg. A highly exothermic chemical reaction system is used to generate on-board electrical power for spacecraft systems, and thermal power to maintain critical spacecraft/lander systems within their allowable flight temperature (AFTs). Based on the very high energy content of the chemical reaction system, a much higher amount of heat per unit mass can be delivered to the spacecraft, relative to a rechargeable lithium-ion battery and electrical heater(s). Since radioisotope heaters or generators are not used, the system will be orders of magnitude lower in cost than a radioisotope heating/power unit, without the attendant regulatory complexities. As part of the CHIPS concept, a fraction of the thermal power generated is converted to electrical power via an appropriate thermal-to-electric converter technology (such as a free piston Stirling converter or a thermoelectric generator module), to provide power to critical loads. This approach is ideally suited to support operation of commercial landers (e.g., via the CLPS program). In most cases, these landers are only designed to operate during a portion of the lunar day, with no provision for survival through the lunar night. By supporting lunar night survival, a mission can be extended through the lunar night and at least into another lunar day, thus turning a nominal eight-day mission into a 36-day mission. Therefore, the current system demonstration will focus on scalability to support at least 336 hours (one lunar night) of continuous thermal and electrical power generation. Although initially targeted to support lunar equatorial landings, the technology is extensible to missions at the lunar poles, other extreme environments in the Solar System or even air-independent applications on Earth (e.g., ocean exploration).

West, William↗

Proton Testing of nVidia Jetson TX1

Single-Event Effects (SEE) testing was conducted on the nVidia Jetson TX1 System on Chip (SOC); herein referred to as device under test (DUT). Testing was conducted at Massachusetts General Hospitals (MGH) Francis H. Burr Proton Therapy Center on October 16th, 2016 using 200MeV protons. This testing trip was purposed to provide a baseline assessment of the radiation susceptibility of the DUT as no previous testing had been conducted on this component.

Proton testing↗

NASA Tech Briefs, February 2012

This issue contains the following briefs: (1) Optical Comb from a Whispering Gallery Mode Resonator for Spectroscopy and Astronomy Instruments Calibration (2) Real-Time Flight Envelope Monitoring System (3) Nemesis Autonomous Test System (4) Mirror Metrology Using Nano-Probe Supports (5) Automated Lab-on-a-Chip Electrophoresis System (6) Techniques for Down-Sampling a Measured Surface Height Map for Model Validation (7) Multi-Component, Multi-Point Interferometric Rayleigh/Mie Doppler Velocimeter (8) Frequency to Voltage Converter Analog Front-End Prototype (9) Dust-Tolerant Intelligent Electrical Connection System (10) Gigabit Ethernet Asynchronous Clock Compensation FIFO (11) High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA (12) Glovebox for GeoLab Subsystem in HDU1-PEM (13) Modified Process Reduces Porosity when Soldering in Reduced Gravity Environments (14) Use of Functionalized Carbon Nanotubes for Covalent Attachment of Nanotubes to Silicon (15) Flexible Plug Repair for Shuttle Wing Leading Edge (16) Three Dimensionally Interlinked, Dense, Solid Form of Single-Walled CNT Ropes (17) Axel Robotic Platform for Crater and Extreme Terrain Exploration (18) Site Tamper and Material Plow Tool - STAMP (19) Magnetic Interface for Segmented Mirror Assembly (20) Transpiration-Cooled Spacecraft-Insulation-Repair Fasteners (21) Fluorescence-Based Sensor for Monitoring Activation of Lunar Dust (22) Aperture Ion Source (23) Virtual Ultrasound Guidance for Inexperienced Operators (24) Model-Based Fault Diagnosis: Performing Root Cause and Impact Analyses in Real Time (25) Interactive Schematic Integration Within the Propellant System Modeling Environment (26) Magnetic and Electric Field Polarizations of Oblique Magnetospheric Chorus Waves (27) Variable Sampling Mapping.

Source record↗

End-to-End Workflow for Machine-Learning-Based Qubit Readout With QICK and hls4ml

In this article, we present an end-to-end workflow for superconducting qubit readout that embeds codesigned neural networks into the quantum instrumentation control kit (QICK). Capitalizing on the custom firmware and software of the QICK platform, which is built on Xilinx radiofrequency system-on-chip field-programmable gate arrays (FPGAs), we aim to leverage machine learning (ML) to address critical challenges in qubit readout accuracy and scalability. The workflow utilizes the hls4ml package and employs quantization-aware training to translate ML models into hardware-efficient FPGA implementations via user-friendly Python application programming interfaces. We experimentally demonstrate the design, optimization, and integration of an ML algorithm for single transmon qubit readout, achieving 96% single-shot fidelity with a latency of 32.25 ns and less than 16% FPGA lookup table resource utilization. Our results offer the community an accessible workflow to advance ML-driven readout and adaptive control in quantum information processing applications.

42 ENGINEERING↗

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Berger, Richard↗

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗

A Novel RF Architecture for Simultaneous Communication, Navigation, and Remote Sensing with Software-Defined Radio

The rapid growth of SmallSat and CubeSat missions at NASA has necessitated a re-evaluation of communication and remote-sensing architectures. Novel designs for CubeSat-sized single-board computers can now include larger Field-Programmable Gate Arrays (FPGAs) and faster System-on-Chip (SoCs) devices. These components substantially improve onboard processing capabilities so that varying subsystems no longer require an independent processor. By replacing individual Radio Frequency (RF) systems with a single software-defined radio (SDR) and processor, mission designers have greater control over reliability, performance, and efficiency. The presented architecture combines individual processing systems into a single design and establishes a modular SDR architecture capable of both remote-sensing and communication applications. This new approach based on a multi-input multi-output (MIMO) SDR features a scalable architecture optimized for Size, Weight, Power, and Cost (SWaP-C), with sufficient noise performance and phase-coherence to enable both remote-sensing and navigation applications, while providing a communication solution for simultaneous S-band and X-band transmission. This SDR design is developed around the NASA CubeSat Card Standard (CS2) that provides the required modularity through simplified backplane and interchangeable options for multiple radiation-hardened/tolerant processors. This architecture provides missions with a single platform for high-rate communication and a future platform to develop cognitive radio systems.

Advanced Avionics, Hybrid Processing, Data Process↗

AMD Radeon e9173 Low Power PCIE GPU Single Event Effects Test Report

The AMD Radeon Embedded e9170 Graphics Processing Unit (GPU), notably the e9173 Peripheral Component Interconnect Express (PCIE) variant, is of interest to Artemis generation programs with requirements for graphics rendering, compute, artificial intelligence (Ai) with a constraints-requiring piece-part procurement and power consumption of less than 50W. In addition to collecting heavy ion data on this device, a secondary purpose of this test campaign was to validate video capture hardware and software workflows used with GPU, microprocessor and system-on-chip device testing. Five (5) test patterns from the NEPP Processor Enclave (NPE) test suite were used with the e9173. The test patterns covered the operating system’s (OS) idle contribution towards the cross section, matrix math using tensorflow-rocm, two artificial intelligence models developed at NASA GSFC, and an industry standard GPU benchmarking application called Mesa GLXGears.

NASA Technical Memorandum (TM) test report for pos↗

Noncontaminating technique for making holes in existing process systems

Technique is developed for making cleanly-contoured holes in assembled process systems without introducing chips or other contaminants into system. Technique uses portable equipment and does not require dismantling of system. Method was tested on Inconel, stainless steel, ASTMA-53, and Hastelloy X in all positions.

Hecker, T. P.↗

Thermal Systems Modeling of Chemical Heat Integrated Power Source (CHIPS) to Survive Lunar Night Environments

This paper presents the results of the systems level thermal modeling for a conceptual Chemical Heat Integrated Power Source (CHIPS). This proposed system offers a combined thermal and electrical power source to support survival of spacecraft operating in extreme low temperature lunar environments, without the use of radioisotope-based sources. A conceptual design study has been completed for this system, that uses heat generated by an exothermic chemical reaction in place of radioisotope or electrical heat sources. The goal of the study was to evaluate the feasibility of such a system through thermodynamic and chemical analysis and thermal modeling, and to identify technology gaps to inform a technology development and maturation plan. The specific technical objectives focused on delivery of 90 to 100 Wth thermal power and 30 to 40 We electrical power for 336 hours to a representative Commercial Lunar Payload Services (CLPS) lander, to support lunar surface survival and limited operations through a lunar night. The total system mass was targeted at ≤50 kg. A highly exothermic chemical reaction system is used to generate on-board electrical power for spacecraft systems, and thermal power to maintain critical spacecraft/lander systems within their allowable flight temperature (AFTs). Based on the very high energy content of the chemical reaction system, a much higher amount of heat per unit mass can be delivered to the spacecraft, relative to a rechargeable lithium-ion battery and electrical heater(s). Since radioisotope heaters or generators are not used, the system will be orders of magnitude lower in cost than a radioisotope heating/power unit, without the attendant regulatory complexities. As part of the CHIPS concept, a fraction of the thermal power generated is converted to electrical power via an appropriate thermal-to-electric converter technology (such as a free piston Stirling converter or a thermoelectric generator module), to provide power to critical loads. This approach is ideally suited to support operation of commercial landers (e.g., via the CLPS program). In most cases, these landers are only designed to operate during a portion of the lunar day, with no provision for survival through the lunar night. By supporting lunar night survival, a mission can be extended through the lunar night and at least into another lunar day, thus turning a nominal eight-day mission into a 36-day mission. Therefore, the current system demonstration will focus on scalability to support at least 336 hours (one lunar night) of continuous thermal and electrical power generation. Although initially targeted to support lunar equatorial landings, the technology is extensible to missions at the lunar poles, other extreme environments in the Solar System or even air-independent applications on Earth (e.g., ocean exploration).

West, William↗

Intelligent subsystem interface for modular hardware system

A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Krening, Douglas N.↗