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NASA NTRS2012

NASA Tech Briefs, February 2012

This issue contains the following briefs: (1) Optical Comb from a Whispering Gallery Mode Resonator for Spectroscopy and Astronomy Instruments Calibration (2) Real-Time Flight Envelope Monitoring System (3) Nemesis Autonomous Test System (4) Mirror Metrology Using Nano-Probe Supports (5) Automated Lab-on-a-Chip Electrophoresis System (6) Techniques for Down-Sampling a Measured Surface Height Map for Model Validation (7) Multi-Component, Multi-Point Interferometric Rayleigh/Mie Doppler Velocimeter (8) Frequency to Voltage Converter Analog Front-End Prototype (9) Dust-Tolerant Intelligent Electrical Connection System (10) Gigabit Ethernet Asynchronous Clock Compensation FIFO (11) High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA (12) Glovebox for GeoLab Subsystem in HDU1-PEM (13) Modified Process Reduces Porosity when Soldering in Reduced Gravity Environments (14) Use of Functionalized Carbon Nanotubes for Covalent Attachment of Nanotubes to Silicon (15) Flexible Plug Repair for Shuttle Wing Leading Edge (16) Three Dimensionally Interlinked, Dense, Solid Form of Single-Walled CNT Ropes (17) Axel Robotic Platform for Crater and Extreme Terrain Exploration (18) Site Tamper and Material Plow Tool - STAMP (19) Magnetic Interface for Segmented Mirror Assembly (20) Transpiration-Cooled Spacecraft-Insulation-Repair Fasteners (21) Fluorescence-Based Sensor for Monitoring Activation of Lunar Dust (22) Aperture Ion Source (23) Virtual Ultrasound Guidance for Inexperienced Operators (24) Model-Based Fault Diagnosis: Performing Root Cause and Impact Analyses in Real Time (25) Interactive Schematic Integration Within the Propellant System Modeling Environment (26) Magnetic and Electric Field Polarizations of Oblique Magnetospheric Chorus Waves (27) Variable Sampling Mapping.

Source record↗
NASA NTRS2006

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Berger, Richard↗
NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗
NASA NTRSDate not supplied

A Novel RF Architecture for Simultaneous Communication, Navigation, and Remote Sensing with Software-Defined Radio

The rapid growth of SmallSat and CubeSat missions at NASA has necessitated a re-evaluation of communication and remote-sensing architectures. Novel designs for CubeSat-sized single-board computers can now include larger Field-Programmable Gate Arrays (FPGAs) and faster System-on-Chip (SoCs) devices. These components substantially improve onboard processing capabilities so that varying subsystems no longer require an independent processor. By replacing individual Radio Frequency (RF) systems with a single software-defined radio (SDR) and processor, mission designers have greater control over reliability, performance, and efficiency. The presented architecture combines individual processing systems into a single design and establishes a modular SDR architecture capable of both remote-sensing and communication applications. This new approach based on a multi-input multi-output (MIMO) SDR features a scalable architecture optimized for Size, Weight, Power, and Cost (SWaP-C), with sufficient noise performance and phase-coherence to enable both remote-sensing and navigation applications, while providing a communication solution for simultaneous S-band and X-band transmission. This SDR design is developed around the NASA CubeSat Card Standard (CS2) that provides the required modularity through simplified backplane and interchangeable options for multiple radiation-hardened/tolerant processors. This architecture provides missions with a single platform for high-rate communication and a future platform to develop cognitive radio systems.

Advanced Avionics, Hybrid Processing, Data Process↗
NASA NTRS2022

AMD Radeon e9173 Low Power PCIE GPU Single Event Effects Test Report

The AMD Radeon Embedded e9170 Graphics Processing Unit (GPU), notably the e9173 Peripheral Component Interconnect Express (PCIE) variant, is of interest to Artemis generation programs with requirements for graphics rendering, compute, artificial intelligence (Ai) with a constraints-requiring piece-part procurement and power consumption of less than 50W. In addition to collecting heavy ion data on this device, a secondary purpose of this test campaign was to validate video capture hardware and software workflows used with GPU, microprocessor and system-on-chip device testing. Five (5) test patterns from the NEPP Processor Enclave (NPE) test suite were used with the e9173. The test patterns covered the operating system’s (OS) idle contribution towards the cross section, matrix math using tensorflow-rocm, two artificial intelligence models developed at NASA GSFC, and an industry standard GPU benchmarking application called Mesa GLXGears.

NASA Technical Memorandum (TM) test report for pos↗
NASA NTRS1972

Noncontaminating technique for making holes in existing process systems

Technique is developed for making cleanly-contoured holes in assembled process systems without introducing chips or other contaminants into system. Technique uses portable equipment and does not require dismantling of system. Method was tested on Inconel, stainless steel, ASTMA-53, and Hastelloy X in all positions.

Hecker, T. P.↗
NASA NTRS2021

Thermal Systems Modeling of Chemical Heat Integrated Power Source (CHIPS) to Survive Lunar Night Environments

This paper presents the results of the systems level thermal modeling for a conceptual Chemical Heat Integrated Power Source (CHIPS). This proposed system offers a combined thermal and electrical power source to support survival of spacecraft operating in extreme low temperature lunar environments, without the use of radioisotope-based sources. A conceptual design study has been completed for this system, that uses heat generated by an exothermic chemical reaction in place of radioisotope or electrical heat sources. The goal of the study was to evaluate the feasibility of such a system through thermodynamic and chemical analysis and thermal modeling, and to identify technology gaps to inform a technology development and maturation plan. The specific technical objectives focused on delivery of 90 to 100 Wth thermal power and 30 to 40 We electrical power for 336 hours to a representative Commercial Lunar Payload Services (CLPS) lander, to support lunar surface survival and limited operations through a lunar night. The total system mass was targeted at ≤50 kg. A highly exothermic chemical reaction system is used to generate on-board electrical power for spacecraft systems, and thermal power to maintain critical spacecraft/lander systems within their allowable flight temperature (AFTs). Based on the very high energy content of the chemical reaction system, a much higher amount of heat per unit mass can be delivered to the spacecraft, relative to a rechargeable lithium-ion battery and electrical heater(s). Since radioisotope heaters or generators are not used, the system will be orders of magnitude lower in cost than a radioisotope heating/power unit, without the attendant regulatory complexities. As part of the CHIPS concept, a fraction of the thermal power generated is converted to electrical power via an appropriate thermal-to-electric converter technology (such as a free piston Stirling converter or a thermoelectric generator module), to provide power to critical loads. This approach is ideally suited to support operation of commercial landers (e.g., via the CLPS program). In most cases, these landers are only designed to operate during a portion of the lunar day, with no provision for survival through the lunar night. By supporting lunar night survival, a mission can be extended through the lunar night and at least into another lunar day, thus turning a nominal eight-day mission into a 36-day mission. Therefore, the current system demonstration will focus on scalability to support at least 336 hours (one lunar night) of continuous thermal and electrical power generation. Although initially targeted to support lunar equatorial landings, the technology is extensible to missions at the lunar poles, other extreme environments in the Solar System or even air-independent applications on Earth (e.g., ocean exploration).

West, William↗
NASA NTRS2000

Intelligent subsystem interface for modular hardware system

A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Krening, Douglas N.↗
NASA NTRS1997

A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

Fang, Wai-Chi↗
NASA NTRS2018

Standardizing GPU Radiation Test Approaches

While some Graphical Processing Units (GPUs) are discrete components (i.e.GTX1050), others take the form of an IP block or embedded engine within a System on Chip (SoC) device such as the Qualcomm Snapdragon"TM" 820 which contains a Qualcomm Adreno"TM" 530 GPU. Within this device are various functional blocks which can be exercised with software payloads. NVidia's Jetson"TM" TX1 SoC is provided on a System on Module (SOM). Within it are Central Processing Unit (CPU) cores and an nVidia GPU which can be accessed similarly to a discrete GPU coprocessor. While the packaging is different, each one of these GPUs needs to be tested using the same standardized code.

Single Event Effects (SEE)↗
NASA NTRS2001

Electrically Isolating Subsystems in SOAC Technologies

Integrated circuit fabrication technology has evolved to the point that it is possible to construct complete systems, including power, data processing, and communications, on a single chip. Such System-on-a-chip (SOAC) technologies can enable drastic reductions in spacecraft size and weight, lowering the cost of missions and presenting new mission opportunities. This paper overviews some key enabling technologies unique to the needs of spacecraft for outer-planet exploration and missions requiring extreme resistance to radiation such as Europa orbiters and Europa Landers. The work is being carried out by Kansas State University (KSU) under direction of the Center for Integrated Space Microsystems (CISM) at NASA's Jet Propulsion Laboratory. Additional information is contained in the original extended abstract.

Boyd, R. M.↗
NASA NTRS2004

Microtechnology in Space: NASA's Lab-on-a-Chip Applications Development Program

NASA's Marshall Space Flight Center (MSFC) Lab on a Chip Application Development LOCAD) team has worked with microfluidic technology for the past few years in an effort to support NASA's Mission. In that time, such microfluidic based Lab-on-a-Chip (LOC) systems have become common technology in clinical and diagnostic laboratories. The approach is most attractive due to its highly miniaturized platform and ability to perform reagent handling (i-e., dilution, mixing, separation) and diagnostics for multiple reactions in an integrated fashion. LOCAD, along with Caliper Life Sciences has successfully developed the first LOC device for macromolecular crystallization using a workstation acquired specifically for designing custom chips, the Caliper 42. LOCAD uses this, along with a novel MSFC-designed and built workstation for microfluidic development. The team has a cadre of LOC devices that can be used to perform initial feasibility testing to determine the efficacy of the LOC approach for a specific application. Once applicability has been established, the LOCAD team, along with the Army's Aviation and Missile Command microfabrication facility, can then begin to custom design and fabricate a device per the user's specifications. This presentation will highlight the LOCAD team's proven and unique expertise that has been utilized to provide end to end capabilities associated with applying microfluidics for applications that include robotic life detection instrumentation, crew health monitoring and microbial and environmental monitoring for human Exploration.

Monaco, Lisa↗
NASA NTRS1987

Survey of current correlators and applications

With this summary an attempt is made to contact as many users as possible so as to provide summary data on correlation systems, both in use and as planned. Data on currently available very large scale integration (VLSI) chips and complete systems are included. Also, several planned correlator systems are described and summarized in tabular form. Finally, a description is given of the work being done in the Communications Systems Research Section on VLSI correlator chips and complete correlator systems.

Lahmeyer, C. R.↗
NASA NTRS1987

IRAC test report. Gallium doped silicon band 2: Read noise and dark current

A direct readout infrared detector array, a candidate for the Space Infrared Telescope Facility (SIRTF) Infrared Array Camera (IRAC), has been tested. The array has a detector surface of gallium doped silicon, bump bonded to a 58x62 pixel MOSFET multiplexer on a separate chip. Although this chip and system do not meet all the SIRTF requirements, the critically important read noise is within a factor of 3 of the requirement. Significant accomplishments of this study include: (1) development of a low noise correlated double sampling readout system with a readout noise of 127 to 164 electrons (based on the detector integrator capacitance of 0.1 pF); (2) measurement of the readout noise of the detector itself, ranging from 123 to 214 electrons with bias only (best to worst pixel), and 256 to 424 electrons with full clocking in normal operation at 5.4 K where dark current is small. Thirty percent smaller read noises are obtained at a temperature of 15K; (3) measurement of the detector response versus integration time, showing significant nonlinear behavior for large signals, well below the saturation level; and (4) development of a custom computer interface and suitable software for collection, analysis and display of data.

Lamb, Gerald↗
NASA NTRS1998

Advanced Exploration Technologies: Micro and Nano Technologies Enabling Space Missions in the 21st Century

Some of the many new and advanced exploration technologies which will enable space missions in the 21st century and specifically the Manned Mars Mission are explored in this presentation. Some of these are the system on a chip, the Computed-Tomography imaging Spectrometer, the digital camera on a chip, and other Micro Electro Mechanical Systems (MEMS) technology for space. Some of these MEMS are the silicon micromachined microgyroscope, a subliming solid micro-thruster, a micro-ion thruster, a silicon seismometer, a dewpoint microhygrometer, a micro laser doppler anemometer, and tunable diode laser (TDL) sensors. The advanced technology insertion is critical for NASA to decrease mass, volume, power and mission costs, and increase functionality, science potential and robustness.

Krabach, Timothy↗
NASA NTRS2002

Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. In this paper we describe the design of Gilgamesh, a PIM-based massively parallel architecture, and elements of its execution model. Gilgamesh extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on macroservers, a middleware layer which supports object-based runtime management of data and threads allowing explicit and dynamic control of locality and load balancing. The paper concludes with a discussion of related research activities and an outlook to future work.

management locality load balance↗
NASA NTRS2007

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗
NASA NTRS2007

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗