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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 919 records · Page 51

Dynamic programming on a shared-memory multiprocessor

Three new algorithms for solving dynamic programming problems on a shared-memory parallel computer are described. All three algorithms attempt to balance work load, while keeping synchronization cost low. In particular, for a multiprocessor having p processors, an analysis of the best algorithm shows that the arithmetic cost is O(n-cubed/6p) and that the synchronization cost is O(absolute value of log sub C n) if p much less than n, where C = (2p-1)/(2p + 1) and n is the size of the problem. The low synchronization cost is important for machines where synchronization is expensive. Analysis and experiments show that the best algorithm is effective in balancing the work load and producing high efficiency.

Edmonds, Phil↗

Field Programmable Gate Array Data Capture for Control Systems

Some Industrial Control Systems (ICS) networks are based on protocols such as Serial and Industrial Ethernet. These protocols currently have no existing cybersecurity monitoring tools, leaving a large gap in the cyber defense of critical infrastructure. In order to analyze such ICS traffic, it is first necessary to implement methods of capturing the ICS data. Whereas traditional methods of analyzing data would use microprocessors, the nature of high-speed analog data can be difficult to implement on such a versatile processor, as they are rather inefficient for doing a single task. Whereas Field Programmable Gate Arrays (FPGAs) provide an adequate tool in analyzing high speed data, as despite the lack of program versatility, Programmable Logic can implement a solution with minimal clock cycles, allowing time for each new packet of data to be captured before a new data sample is taken.

42 ENGINEERING↗

System, method, and computer program for creating an internal conforming structure

A system for creating an internal formation of a tubular structure having an inner surface via additive manufacturing. The system broadly includes a computer modeling system and an additive manufacturing system. The computer modeling system may include a processor for generating a lattice cellular component via computer-aided design software according to inputs received from a user. The processor may also generate an internal formation lattice structure based on the lattice cellular component and modify the lattice structure to follow and/or conform to the curvature of the inner surface of the outer wall of the tubular structure. The additive manufacturing system may be configured to produce the lattice structure and the tubular structure via additive manufacturing material deposited layer by layer according to the lattice structure.

42 ENGINEERING↗

4-Clique network minor embedding for quantum annealers

Quantum annealing is a quantum algorithm for computing solutions to combinatorial optimization problems. This study proposes a method for minor embedding optimization problems onto sparse quantum annealing hardware graphs called 4-clique network minor embedding. This method is in contrast to the standard minor embedding technique of using a path of linearly connected qubits in order to represent a logical variable state. The 4-clique minor embedding is possible on Pegasus graph connectivity, which is the native hardware graph for some of the current D-Wave quantum annealers. The Pegasus hardware graph contains many cliques of size 4, making it possible to form a graph composed entirely of paths of connected 4-cliques on which a problem can be minor-embedded. The 4-clique chains come at the cost of additional qubit usage on the hardware graph, but they allow for stronger coupling within each chain, thereby increasing chain integrity, reducing chain breaks, and allow for greater usage of the available energy scale for programming logical problem coefficients on current quantum annealers. The 4-clique minor embedding technique is compared with the standard linear path minor embedding with experiments on two D-Wave quantum annealing processors with Pegasus hardware graphs. We show proof-of-concept experiments where the 4-clique minor embeddings can use weak chain strengths while successfully carrying out the computation of minimizing random all-to-all spin glass problem instances. Published by the American Physical Society 2024

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Feasibility study for a numerical aerodynamic simulation facility. Volume 3: FMP language specification/user manual

The manual is intended to show the revisions and additions to the current STAR FORTRAN. The changes are made to incorporate an FMP (Flow Model Processor) for use in the Numerical Aerodynamic Simulation Facility (NASF) for the purpose of simulating fluid flow over three-dimensional bodies in wind tunnel environments and in free space. The FORTRAN programming language for the STAR-100 computer contains both CDC and unique STAR extensions to the standard FORTRAN. Several of the STAR FORTRAN extensions to standard FOR-TRAN allow the FORTRAN user to exploit the vector processing capabilities of the STAR computer. In STAR FORTRAN, vectors can be expressed with an explicit notation, functions are provided that return vector results, and special call statements enable access to any machine instruction.

Kenner, B. G.↗

Environmental projects, volume 11. Environmental assessment: Addition to operations building, Mars site

An Environmental Assessment was performed of the proposed addition to building G-86 at the Mars Site, which will provide space for new electronic equipment to consolidate the Deep Space Network (DSN) support facilities from other Goldstone Deep Space Communication Complex (GDSCC) sites at the Mars Site, and will include a fifth telemetry and command group with its associated link monitor, control processor, and operator consoles. The addition of these facilities will increase the capability of the DSN to support future sophisticated NASA spacecraft missions such as the International Solar and Terrestrial Physics (ISTP) Program. The planned construction of this building addition requires an Environmental Assessment (EA) document that records the existing environmental conditions at the Mars Site, that analyzes the environmental effects that possibly could be expected from the construction and use of the new building addition, and that recommends measures to be taken to mitigate any possible deleterious environmental effects.

Source record↗

Compiling global name-space parallel loops for distributed execution

Distributed memory machines do not provide hardware support for a global address space. Thus programmers are forced to partition the data across the memories of the architecture and use explicit message passing to communicate data between processors. The compiler support required to allow programmers to express their algorithms using a global name-space is examined. A general method is presented for analysis of a high level source program and its translation into a set of independently executing tasks communicating via messages. If the compiler has enough information, this translation can be carried out at compile time. Otherwise, run-time code is generated to implement the required data movement. The analysis required in both situations is described and the performance of the generated code on the Intel iPSC/2 is presented.

Koelbel, Charles↗

Geopotential Error Analysis from Satellite Gradiometer and Global Positioning System Observables on Parallel Architecture

The recovery of a high resolution geopotential from satellite gradiometer observations motivates the examination of high performance computational techniques. The primary subject matter addresses specifically the use of satellite gradiometer and GPS observations to form and invert the normal matrix associated with a large degree and order geopotential solution. Memory resident and out-of-core parallel linear algebra techniques along with data parallel batch algorithms form the foundation of the least squares application structure. A secondary topic includes the adoption of object oriented programming techniques to enhance modularity and reusability of code. Applications implementing the parallel and object oriented methods successfully calculate the degree variance for a degree and order 110 geopotential solution on 32 processors of the Cray T3E. The memory resident gradiometer application exhibits an overall application performance of 5.4 Gflops, and the out-of-core linear solver exhibits an overall performance of 2.4 Gflops. The combination solution derived from a sun synchronous gradiometer orbit produce average geoid height variances of 17 millimeters.

Schutz, Bob E.↗

Efficient implementation of the many-body Reactive Bond Order (REBO) potential on GPU

The second generation Reactive Bond Order (REBO) empirical potential is commonly used to accurately model a wide range hydrocarbon materials. It is also extensible to other atom types and interactions. REBO potential assumes complex multi-body interaction model, that is difficult to represent efficiently in the SIMD or SIMT programming model. Hence, despite its importance, no efficient GPGPU implementation has been developed for this potential. Here we present a detailed description of a highly efficient GPGPU implementation of molecular dynamics algorithm using REBO potential. The presented algorithm takes advantage of rarely used properties of the SIMT architecture of a modern GPU to solve difficult synchronizations issues that arise in computations of multi-body potential. Techniques developed for this problem may be also used to achieve efficient solutions of different problems. The performance of proposed algorithm is assessed using a range of model systems. It is compared to highly optimized CPU implementation (both single core and OpenMP) available in LAMMPS package. These experiments show up to 6x improvement in forces computation time using single processor of the NVIDIA Tesla K80 compared to high end 16-core Intel Xeon processor.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

A Hybrid FPGA/Tilera Compute Element for Autonomous Hazard Detection and Navigation

To increase safety for future missions landing on other planetary or lunar bodies, the Autonomous Landing and Hazard Avoidance Technology (ALHAT) program is developing an integrated sensor for autonomous surface analysis and hazard determination. The ALHAT Hazard Detection System (HDS) consists of a Flash LIDAR for measuring the topography of the landing site, a gimbal to scan across the terrain, and an Inertial Measurement Unit (IMU), along with terrain analysis algorithms to identify the landing site and the local hazards. An FPGA and Manycore processor system was developed to interface all the devices in the HDS, to provide high-resolution timing to accurately measure system state, and to run the surface analysis algorithms quickly and efficiently. In this paper, we will describe how we integrated COTS components such as an FPGA evaluation board, a TILExpress64, and multi-threaded/multi-core aware software to build the HDS Compute Element (HDSCE). The ALHAT program is also working with the NASA Morpheus Project and has integrated the HDS as a sensor on the Morpheus Lander. This paper will also describe how the HDS is integrated with the Morpheus lander and the results of the initial test flights with the HDS installed. We will also describe future improvements to the HDSCE.

Multicore↗

A hybrid FPGA/Tilera compute element for autonomous hazard detection and navigation

To increase safety for future missions landing on other planetary or lunar bodies, the Autonomous Landing and Hazard Avoidance Technology (ALHAT) program is developing an integrated sensor for autonomous surface analysis and hazard determination. The ALHAT Hazard Detection System (HDS) consists of a Flash LIDAR for measuring the topography of the landing site, a gimbal to scan across the terrain, and an Inertial Measurement Unit (IMU), along with terrain analysis algorithms to identify the landing site and the local hazards. An FPGA and Manycore processor system was developed to interface all the devices in the HDS, to provide high-resolution timing to accurately measure system state, and to run the surface analysis algorithms quickly and efficiently. In this paper, we will describe how we integrated COTS components such as an FPGA evaluation board, a TILExpress64, and multi-threaded/multi-core aware software to build the HDS Compute Element (HDSCE). The ALHAT program is also working with the NASA Morpheus Project and has integrated the HDS as a sensor on the Morpheus Lander. This paper will also describe how the HDS is integrated with the Morpheus lander and the results of the initial test flights with the HDS installed. We will also describe future improvements to the HDSCE.

Trawny, Nikolas↗

Cartography: LACIE's spatial processor

The spatial processing needs of LACIE include the location of agricultural test sites, and the registration of ground truth to LANDSAT imagery. The technological aspects of LACIE cartographic support, the need for cartography in satellite crop surveys, and proposed improvements which would enhance support of future programs are discussed.

Rader, M. L.↗

Biomedical engineering tasks

Electrocardiographic and vectorcardiographic bioinstrumentation work centered on the development of a new electrode system harness for Project Skylab. Evaluation of several silver electrode configurations proved superior impedance voltage performance for silver/silver chloride electrodes mounted flush by using a paste adhesive. A portable ECG processor has been designed and a breadboard unit has been built to sample ECG input data at a rate of 500 samples per second for arrhythmia detection. A small real time display driver program has been developed for statistical analysis on selected QPS features. Engineering work on a sleep monitoring cap assembly continued.

Source record↗

Editing of EIA coded, numerically controlled, machine tool tapes

Editing of numerically controlled (N/C) machine tool tapes (8-level paper tape) using an interactive graphic display processor is described. A rapid technique required for correcting production errors in N/C tapes was developed using the interactive text editor on the IMLAC PDS-ID graphic display system and two special programs resident on disk. The correction technique and special programs for processing N/C tapes coded to EIA specifications are discussed.

Weiner, J. M.↗

Data Management Symposium, Huntsville, Ala., October 18, 19, 1977, Proceedings

The transfer, processing, and use of satellite data are discussed. Topics relating to simulation and processing techniques include computer design assessments through simulation, data system dynamic simulation, and future timing accuracy requirements and procedures for data processing. Subjects relevant to data base management systems and users and their needs include an image-based information system architecture for correlation satellite and topological data base, efficient searching and sorting applications using an associative array processor, analysis of user's needs for a large technical data base, and variable length data formats. The technology development outlook was considered with attention to data systems technology outlook for supporting NASA programs, a user-oriented interactive information extraction system, and flow control and sorting techniques for telemetry packets.

Castelli, A.↗

Expert system for multidisciplinary analysis and optimization using ASTROS

This paper discusses the framework of a Knowledge Based Expert System (KBES) environment to design aerospace structures under structural and aerodynamic constraints using ASTROS (Automated Structural Optimization program). ASTROS is a synthesis tool built around the NASTRAN finite element program. The knowledge base capabilities are discussed for synthesizing in statics, normal mode, steady and unsteady aerodynamic disciplines. A description of the two ASTROS advisor modules the Editor/Bulk Data generator and Post-processor is included. Experiences and issues involved in hierarchical representation of knowledge as menu options at different levels of abstraction are presented. A brief overview of Knowledge Based Systems and the shell CLIPS (C Language Integrated Production System) used to develop the ASTROS Advisor are discussed. Illustrative examples of the advisor in designing airframe structures are also included.

Sarma, Hari K.↗

Advanced End-to-end Simulation for On-board Processing (AESOP)

Developers of data compression algorithms typically use their own software together with commercial packages to implement, evaluate and demonstrate their work. While convenient for an individual developer, this approach makes it difficult to build on or use another's work without intimate knowledge of each component. When several people or groups work on different parts of the same problem, the larger view can be lost. What's needed is a simple piece of software to stand in the gap and link together the efforts of different people, enabling them to build on each other's work, and providing a base for engineers and scientists to evaluate the parts as a cohesive whole and make design decisions. AESOP (Advanced End-to-end Simulation for On-board Processing) attempts to meet this need by providing a graphical interface to a developer-selected set of algorithms, interfacing with compiled code and standalone programs, as well as procedures written in the IDL and PV-Wave command languages. As a proof of concept, AESOP is outfitted with several data compression algorithms integrating previous work on different processors (AT&T DSP32C, TI TMS320C30, SPARC). The user can specify at run-time the processor on which individual parts of the compression should run. Compressed data is then fed through simulated transmission and uncompression to evaluate the effects of compression parameters, noise and error correction algorithms. The following sections describe AESOP in detail. Section 2 describes fundamental goals for usability. Section 3 describes the implementation. Sections 4 through 5 describe how to add new functionality to the system and present the existing data compression algorithms. Sections 6 and 7 discuss portability and future work.

Mazer, Alan S.↗

Communication overhead on the Intel Paragon, IBM SP2 and Meiko CS-2

Interprocessor communication overhead is a crucial measure of the power of parallel computing systems-its impact can severely limit the performance of parallel programs. This report presents measurements of communication overhead on three contemporary commercial multicomputer systems: the Intel Paragon, the IBM SP2 and the Meiko CS-2. In each case the time to communicate between processors is presented as a function of message length. The time for global synchronization and memory access is discussed. The performance of these machines in emulating hypercubes and executing random pairwise exchanges is also investigated. It is shown that the interprocessor communication time depends heavily on the specific communication pattern required. These observations contradict the commonly held belief that communication overhead on contemporary machines is independent of the placement of tasks on processors. The information presented in this report permits the evaluation of the efficiency of parallel algorithm implementations against standard baselines.

Bokhari, Shahid H.↗