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At least 955 records · Page 53

Gaussian approximation versus nearly exact performance analysis of optical communication systems with PPM signaling and APD receivers

A 25-Mb/s direct-detection optical communication system that used Q = 4 PPM (pulse-position modulation) signaling was constructed and its performance measured under laboratory conditions. The system used a single-mode AlGaAs laser diode (lambda = 834 nm) and low-noise silicon avalanche photodiode (APD). A procedure for numerically computing system performance is given that uses the nearly exact Webb approximation of the true Conradi distribution for the APD output and does not require excessive amounts of computer time. Comparison revealed that modeling the APD ouptut as a Gaussian process under conditions of negligible background radiation and low (less than 10 to the -12 A) APD bulk leakage currents leads to substantial underestimates of optimal APD gain and overestimates of system bit error probability. Examples illustrate the breakdown of the Gaussian approximation in assessing system performance. The measured performance was in excellent agreement with that predicted by the computational procedure. The system achieved a bit error probability of 10 to the -6 at a received signal energy, corresponding to an average of 60 absorbed photons/bit and optimal APD gain of 700.

Davidson, Frederic M.↗

BLITZEN - A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗

Halftoning method for the generation of motion stimuli

This paper describes a novel computer-graphic technique for the generation of a broad class of motion stimuli for vision research, which uses color table animation in conjunction with a single base image. Using this technique, contrast and temporal frequency can be varied with a negligible amount of computation, once a single-base image is produced. Since only two-bit planes are needed to display a single drifting grating, an eight-bit/pixel display can be used to generate four-component plaids, in which each component of the plaid has independently programmable contrast and temporal frequency. Because the contrast and temporal frequencies of the various components are mutually independent, a large number of two-dimensional stimulus motions can be produced from a single image file.

Mulligan, Jeffrey B.↗

Asymmetric Memory Circuit Would Resist Soft Errors

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Buehler, Martin G.↗

Peripheral Equipment Interchanges Bytes Of Data

Method for conversion of data formats between incompatible computers reduces conversion time by 80 percent. Transposes high and low bytes of word so data from computer A match storage format of computer B. Two interface circuit boards convert data. Such boards ordinarily used for communication between computers. In format-conversion application, cable connecting boards modified so high-8-bit and low-8-bit data lines interchanged with result data words in proper format for computer B.

Aguilar, Robert B.↗

Programmable Direct-Memory-Access Controller

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Hendry, David F.↗

Large-Constraint-Length, Fast Viterbi Decoder

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

Collins, O.↗

Context dependent prediction and category encoding for DPCM image compression

Efficient compression of image data requires the understanding of the noise characteristics of sensors as well as the redundancy expected in imagery. Herein, the techniques of Differential Pulse Code Modulation (DPCM) are reviewed and modified for information-preserving data compression. The modifications include: mapping from intensity to an equal variance space; context dependent one and two dimensional predictors; rationale for nonlinear DPCM encoding based upon an image quality model; context dependent variable length encoding of 2x2 data blocks; and feedback control for constant output rate systems. Examples are presented at compression rates between 1.3 and 2.8 bits per pixel. The need for larger block sizes, 2D context dependent predictors, and the hope for sub-bits-per-pixel compression which maintains spacial resolution (information preserving) are discussed.

Beaudet, Paul R.↗

Image gathering and coding for digital restoration: Information efficiency and visual quality

Image gathering and coding are commonly treated as tasks separate from each other and from the digital processing used to restore and enhance the images. The goal is to develop a method that allows us to assess quantitatively the combined performance of image gathering and coding for the digital restoration of images with high visual quality. Digital restoration is often interactive because visual quality depends on perceptual rather than mathematical considerations, and these considerations vary with the target, the application, and the observer. The approach is based on the theoretical treatment of image gathering as a communication channel (J. Opt. Soc. Am. A2, 1644(1985);5,285(1988). Initial results suggest that the practical upper limit of the information contained in the acquired image data range typically from approximately 2 to 4 binary information units (bifs) per sample, depending on the design of the image-gathering system. The associated information efficiency of the transmitted data (i.e., the ratio of information over data) ranges typically from approximately 0.3 to 0.5 bif per bit without coding to approximately 0.5 to 0.9 bif per bit with lossless predictive compression and Huffman coding. The visual quality that can be attained with interactive image restoration improves perceptibly as the available information increases to approximately 3 bifs per sample. However, the perceptual improvements that can be attained with further increases in information are very subtle and depend on the target and the desired enhancement.

Huck, Friedrich O.↗

BLITZEN: A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗

Quantization effects in Viterbi decoding rate 1/n convolutional codes

A Viterbi decoder's performance loss due to quantizing data from the additive white Gaussian noise (AWGN) channel is studied. An optimal quantization scheme and branch metric calculation method are presented. The uniformly quantized channel capacity C(sub u)(q) is used to determine the smallest number of quantization bits q that does not cause a significant loss. The quantizer stepsize which maximizes C(sub u)(q) almost minimizes the decoder bit error rate (BER). However, a slightly larger stepsize is better, like the value that minimizes the Bhattacharyya bound. The range and renormalization of state metrics is analyzed, in particular for K = 15 decoders such as the Big Viterbi Decoder (BVD) for the Galileo mission. These results are required to design reduced hardware complexity Viterbi decoders with a negligible quantization loss.

Onyszchuk, I. M.↗

Direct detection optical intersatellite link at 220 Mbps using AlGaAs laser diode and silicon APD with 4-ary PPM signaling

A newly developed 220 Mbps free-space 4-ary pulse position modulation (PPM) direct detection optical communication system is described. High speed GaAs integrated circuits were used to construct the PPM encoder and receiver electronic circuits. Both PPM slot and word timing recovery were provided in the PPM receiver. The optical transmitter consisted of an AlGaAs laser diode (Mitsubishi ML5702A, lambda=821nm) and a high speed driver unit. The photodetector consisted of a silicon avalanche photodiode (APD) (RCA30902S) preceded by an optical interference filter (delta lambda=10nm). Preliminary tests showed that the self-synchronized PPM receiver could achieve a receiver bit error rate of less than 10(exp -6) at 25 nW average received optical signal power or 360 photons per transmitted information bit. The relatively poor receiver sensitivity was believed to be caused by the insufficient electronic bandwidth of the APD preamplifier and the poor linearity of the preamplifier high frequency response.

Sun, Xiaoli↗

A few modeling and rendering techniques for computer graphics and their implementation on ultra hardware

Ultra network is a recently installed very high speed graphic hardware at NASA Langley Research Center. The Ultra Network interfaced to Voyager through its HSX channel is capable of transmitting up to 800 million bits of information per second. It is capable of displaying fifteen to twenty frames of precomputed images of size 1024 x 2368 with 24 bits of color information per pixel per second. Modeling and rendering techniques are being developed in computer graphics and implemented on Ultra hardware. A ray tracer is being developed for use at the Flight Software and Graphic branch. Changes were made to make the ray tracer compatible with Voyager.

Bidasaria, Hari↗

Lunar deep drill apparatus

A self contained, mobile drilling and coring system was designed to operate on the Lunar surface and be controlled remotely from earth. The system uses SKITTER (Spatial Kinematic Inertial Translatory Tripod Extremity Robot) as its foundation and produces Lunar core samples two meters long and fifty millimeters in diameter. The drill bit used for this is composed of 30 per carat diamonds in a sintered tungsten carbide matrix. To drill up to 50 m depths, the bit assembly will be attached to a drill string made from 2 m rods which will be carried in racks on SKITTER. Rotary power for drilling will be supplied by a Curvo-Synchronous motor. SKITTER is to support this system through a hexagonal shaped structure which will contain the drill motor and the power supply. A micro-coring drill will be used to remove a preliminary sample 5 mm in diameter and 20 mm long from the side of the core. This whole system is to be controlled from earth. This is carried out by a continuously monitoring PLC onboard the drill rig. A touch screen control console allows the operator on earth to monitor the progress of the operation and intervene if necessary.

Harvey, Jill↗

The role of the + or - 1 number system in multibit hardware correlators

The use of commercially available 1-bit LSI correlator chips whose main function is the correlation of sequences of plus ones and minus ones (rather than zeros and ones) as building blocks in the design of multibit correlators is investigated. A radix-2 number system in which the bit values are + or - 1 (no zero) is discussed. The development of a simple conversion algorithm to find the + or - 1 representation of a number given in 2's complement is presented. Some of the issues raised by this conversion algorithm are discussed. It is shown that, if the analog signal is available, there is a simple step to take before the analog-to-digital conversion in order to improve the overall precision. The construction of multibit correlators based on the + or - 1 system is compared to alternative approaches.

Zohar, Shalhav↗

Wavelength division multiplexed fiber optic absolute position encoder

A wavelength division multiplexing (WDM) method for fiber optic sensors is proposed which uses a broadband light source and narrow bandpass thin film optical filter coatings on cylindrical graded index lenses. In the WDM system described here, all bits are multiplexed onto a single signal return fiber by assigning each bit a unique wavelength. A multielement photodetector array is used as the encoded position information is in parallel. Preliminary prototype test results are presented.

Park, Eric D.↗

A quasi-passive CMOS pipeline D/A converter

A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.

Wang, Fong-Jim↗

Adaptive box filters for removal of random noise from digital images

Adaptive box-filtering algorithms to remove random bit errors and to smooth noisy data have been developed. For both procedures, the standard deviation of those pixels within a local box surrounding each pixel is used. A series of two or three filters with decreasing box sizes can be run to clean up extremely noisy images and to remove bit errors near sharp edges. The second filter, for noise smoothing, is similar to the 'sigma filter' of Lee (1983). The technique effectively reduces speckle in radar images without eliminating fine details.

Eliason, Eric M.↗