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All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗
DOE OSTI2023

Boards having solderless interconnects

This disclosure provides systems, methods, and apparatus related to printed circuit boards. In one aspect, a device includes a first board and a second board. The first board includes at least two pins defined at an end of the first board. The first pin and the second pin are positioned along a first line and parallel to the first line. The second board includes at least two slots defined at an end of the second board. The first slot and the second slot are positioned along a second line and are angled from the second line by about ±10° to 15°. Each of the pins in the first board is engaged with each of the slots in the second board and forms an electrical connection between the first pin and the first slot and the second pin and the second slot.

Wielandt, Stijn↗