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An efficient three dimensional unstructured Euler solver is parallelized on a Cray Y-MP C90 shared memory computer and on an Intel Touchstone Delta distributed memory computer. This paper relates the experiences gained and describes the software tools and hardware used in this study. Performance comparisons between two differing architectures are made.
For the purpose of reducing the spurious states in a Hopfield neural net for associative memory, we invoke terminal attractors. In achieving the optical implementation of the terminal-attractor-based associative memory (TABAM) as described in this paper, we first prove the existence of the terminal-attractor model with binary neuron representation. We then present several one- and two-dimensional optical architectures for the TABAM. Finally, as an example, we experimentally demonstrate an inner-product optical neural model using liquid-crystal spatial light modulators with engineering approximations and discuss how to apply the inner-product model to build a two-dimensional parallel processing TABAM.
In this paper, we examine how disk arrays and shared memory multiprocessors lead to an effective method for constructing database machines for general-purpose complex query processing. We show that disk arrays can lead to cost-effective storage systems if they are configured from suitably small formfactor disk drives. We introduce the storage system metric data temperature as a way to evaluate how well a disk configuration can sustain its workload, and we show that disk arrays can sustain the same data temperature as a more expensive mirrored-disk configuration. We use the metric to evaluate the performance of disk arrays in XPRS, an operational shared-memory multiprocessor database system being developed at the University of California, Berkeley.
Potentially narrow margins of chirality-based chopping of magnetic stripes avoided. Half-state readout is experimental method of readout in Vertical-Bloch-Line (VBL) memory. Based on differential deflections of magnetic stripe domains in which data bits stored. To give meaning to explanation of half-state readout, see "Vertical-Bloch-Line Memory" (NPO-18467).
Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.
A unipolar terminal-attractor based neural associative memory (TABAM) system with adaptive threshold for perfect convergence is presented. By adaptively setting the threshold values for the dynamic iteration for the unipolar binary neuron states with terminal-attractors for the purpose of reducing the spurious states in a Hopfield neural network for associative memory and using the inner product approach, perfect convergence and correct retrieval is achieved. Simulation is completed with a small number of stored states (M) and a small number of neurons (N) but a large M/N ratio. An experiment with optical exclusive-OR logic operation using LCTV SLMs shows the feasibility of optoelectronic implementation of the models. A complete inner-product TABAM is implemented using a PC for calculation of adaptive threshold values to achieve a unipolar TABAM (UIT) in the case where there is no crosstalk, and a crosstalk model (CRIT) in the case where crosstalk corrupts the desired state.
This experiment investigated the integrity of static computer memory (floppy disk media) when exposed to the environment of low earth orbit. The experiment attempted to record soft-event upsets (bit-flips) in static computer memory. Typical conditions that exist in low earth orbit that may cause soft-event upsets include: cosmic rays, low level background radiation, charged fields, static charges, and the earth's magnetic field. Over the years several spacecraft have been affected by soft-event upsets (bit-flips), and these events have caused a loss of data or affected spacecraft guidance and control. This paper describes a commercial spin-off that is being developed from the experiment.
An associative optical memory including an input spatial light modulator (SLM) in the form of an edge enhanced liquid crystal light valve (LCLV) and a pair of memory SLM's in the form of liquid crystal televisions (LCTV's) forms a matrix array of an input image which is cross correlated with a matrix array of stored images. The correlation product is detected and nonlinearly amplified to illuminate a replica of the stored image array to select the stored image correlating with the input image. The LCLV is edge enhanced by reducing the bias frequency and voltage and rotating its orientation. The edge enhancement and nonlinearity of the photodetection improves the orthogonality of the stored image. The illumination of the replicate stored image provides a clean stored image, uncontaminated by the image comparison process.
Variability in the methods and models used for single event upset calculations in microelectronic memory devices can lead to a range of possible upset rates. Using heavy ion and proton data for selected DRAM and SRAM memories, we have calculated an array of upset rates in order to compare the Adams worst case interplanetary solar flare model to a model proposed by scientists at the Jet Propulsion Laboratory. In addition, methods of upset rate calculation are compared: the Cosmic Ray Effects on Microelectronics CREME code and a Monte Carlo algorithm developed at the Applied Physics Laboratory. The results show that use of a more realistic, although still conservative, model of the space environment can have significant cost saving benefits.
In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .
The NASA Lewis Research Center is developing a multichannel communication signal processing satellite (MCSPS) system which will provide low data rate, direct to user, commercial communications services. The focus of current space segment developments is a flexible, high-throughput, fault tolerant onboard information switching processor. This information switching processor (ISP) is a destination-directed packet switch which performs both space and time switching to route user information among numerous user ground terminals. Through both industry study contracts and in-house investigations, several packet switching architectures were examined. A contention-free approach, the shared memory per beam architecture, was selected for implementation. The shared memory per beam architecture, fault tolerance insertion, implementation, and demonstration plans are described.
This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.
An efficient three dimensional unstructured Euler solver is parallelized on a Cray Y-MP C90 shared memory computer and on an Intel Touchstone Delta distributed memory computer. This paper relates the experiences gained and describes the software tools and hardware used in this study. Performance comparisons between two differing architectures are made.
We study a high order finite difference scheme to solve the time accurate flow field of a jet using the compressible Navier-Stokes equations. As part of our ongoing efforts, we have implemented our numerical model on three parallel computing platforms to study the computational, communication, and scalability characteristics. The platforms chosen for this study are a cluster of workstations connected through fast networks (the LACE experimental testbed at NASA Lewis), a shared memory multiprocessor (the Cray YMP), and a distributed memory multiprocessor (the IBM SPI). Our focus in this study is on the LACE testbed. We present some results for the Cray YMP and the IBM SP1 mainly for comparison purposes. On the LACE testbed, we study: (1) the communication characteristics of Ethernet, FDDI, and the ALLNODE networks and (2) the overheads induced by the PVM message passing library used for parallelizing the application. We demonstrate that clustering of workstations is effective and has the potential to be computationally competitive with supercomputers at a fraction of the cost.
This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.
A computational strategy is presented for the nonlinear static and postbuckling analyses of large complex structures on massively parallel computers. The strategy is designed for distributed-memory, message-passing parallel computer systems. The key elements of the proposed strategy are: (1) a multiple-parameter reduced basis technique; (2) a nested dissection (or multilevel substructuring) ordering scheme; (3) parallel assembly of global matrices; and (4) a parallel sparse equation solver. The effectiveness of the strategy is assessed by applying it to thermo-mechanical postbuckling analyses of stiffened composite panels with cutouts, and nonlinear large-deflection analyses of HSCT models on Intel Paragon XP/S computers. The numerical studies presented demonstrate the advantages of nested dissection-based solvers over traditional skyline-based solvers on distributed memory machines.
Analytical procedures are developed for a composite system consisting of shape memory alloy fibers within an elastic matrix subject to uniform temperature fluctuations. Micromechanics for the calculation of the equivalent properties of the composite are presented by extending the multi-cell model to incorporate shape memory alloy fibers. A three phase concentric cylinder model is developed for the analysis of local stresses which includes the fiber, the matrix, and the surrounding homogenized composite. The solution addresses the complexities induced by the nonlinear dependence of the in-situ martensite fraction of the fibers to the local stresses and temperature, and the local stresses developed from interactions between the fibers and matrix during the martensitic and reverse phase transformations. Results are presented for a nitinol/epoxy composite. The applications illustrate the response of the composite in isothermal longitudinal loading and unloading, and in temperature induced actuation. The local stresses developed in the composite under various stages of the martensitic and reverse phase transformation are also shown.
Thin film shape memory alloy has been integrated with silicon in a new actuation mechanism for microelectromechanical systems. This paper compares nickel-titanium film with other actuators, describes recent results of chemical milling processes developed to fabricate shape memory alloy microactuators in silicon, and describes simple actuation mechanisms which have been fabricated and tested.