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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,009 records · Page 56

All sources NASA NTRS DOE OSTI

NASA NTRS1988

High conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗

NASA NTRS1988

Method of making a high conductance ohmic junction for monolithic semiconductor devices

Lewis, Carol R.↗

NASA NTRS2010

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.1 and at least one other matrix, with first equation including X.sup.1Y, X.sup.1A, and X.sup.1P, and the second equation including X.sup.1A and X.sup.1P.

Jain, Jitesh↗

NASA NTRS2012

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.-1 and at least one other matrix, with first equation including X.sup.-1Y, X.sup.-1A, and X.sup.-1P, and the second equation including X.sup.-1A and X.sup.-1P.

Jain, Jitesh↗

NASA NTRS2013

Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication

NASAs future exploration missions focus on the manned exploration of the Moon, Mars, and beyond, which will rely heavily on the development of a reliable communications infrastructure from planetary surface-to-surface, surface-to-orbit, and back to Earth. Flexible antennas are highly desired in many scenarios. Active phased array antennas (active PAAs) with distributed control and processing electronics at the surface of an antenna aperture offer numerous advantages for radar communications. Large-area active PAAs on flexible substrates are of particular interest in NASA s space radars due to their efficient inflatable package that can be rolled up during transportation and deployed in space. Such an inflatable package significantly reduces stowage volume and mass. Because of these performance and packaging advantages, large-area inflatable active PAAs are highly desired in NASA s surface-to-orbit and surface-to-relay communications. To address the issues of flexible electronics, a room-temperature printing process of active phased-array antennas on a flexible Kapton substrate was developed. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proved feasible for the PAA system. This innovation is a new type of fully inkjet-printable, two-dimensional, high-frequency PAA on a flexible substrate at room temperature. The designed electronic circuit components, such as the FET switches in the phase shifter, metal interconnection lines, microstrip transmission lines, etc., are all printed using a special inkjet printer. Using the developed technology, entire 1x4, 2x2, and 4x4 PAA systems were developed, packaged, and demonstrated at 5.3 GHz. Several key solutions are addressed in this work to solve the fabrication issues. The source/drain contact is developed using droplets of silver ink printed on the source/drain areas prior to applying CNT thin-film. The wet silver ink droplets allow the silver to wet the CNT thin-film area and enable good contact with the source and drain contact after annealing. A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This film is also used as the media for transferring the aligned CNT thin-film on the device substrate. A simple and cost-effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior to bonding on the first substrate. Inkjet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the bottom layer. It is then annealed to form a good connection. One-dimensional and two-dimensional PAAs were fabricated and characterized. In these circuits, multilayer metal interconnects were used to make a complete PAA system.

Subbaraman, Harish↗

NASA NTRS2014

Computationally Efficient Modeling and Simulation of Large Scale Systems

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Jain, Jitesh↗

NASA NTRS2008

Interfacing Space Communications and Navigation Network Simulation with Distributed System Integration Laboratories (DSIL)

NASA's planned Lunar missions will involve multiple NASA centers where each participating center has a specific role and specialization. In this vision, the Constellation program (CxP)'s Distributed System Integration Laboratories (DSIL) architecture consist of multiple System Integration Labs (SILs), with simulators, emulators, testlabs and control centers interacting with each other over a broadband network to perform test and verification for mission scenarios. To support the end-to-end simulation and emulation effort of NASA' exploration initiatives, different NASA centers are interconnected to participate in distributed simulations. Currently, DSIL has interconnections among the following NASA centers: Johnson Space Center (JSC), Kennedy Space Center (KSC), Marshall Space Flight Center (MSFC) and Jet Propulsion Laboratory (JPL). Through interconnections and interactions among different NASA centers, critical resources and data can be shared, while independent simulations can be performed simultaneously at different NASA locations, to effectively utilize the simulation and emulation capabilities at each center. Furthermore, the development of DSIL can maximally leverage the existing project simulation and testing plans. In this work, we describe the specific role and development activities at JPL for Space Communications and Navigation Network (SCaN) simulator using the Multi-mission Advanced Communications Hybrid Environment for Test and Evaluation (MACHETE) tool to simulate communications effects among mission assets. Using MACHETE, different space network configurations among spacecrafts and ground systems of various parameter sets can be simulated. Data that is necessary for tracking, navigation, and guidance of spacecrafts such as Crew Exploration Vehicle (CEV), Crew Launch Vehicle (CLV), and Lunar Relay Satellite (LRS) and orbit calculation data are disseminated to different NASA centers and updated periodically using the High Level Architecture (HLA). In addition, the performance of DSIL under different traffic loads with different mix of data and priorities are evaluated.

Traffic Measuring and Monitoring↗

NASA NTRSDate not supplied

Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments

This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.

Silicon Carbide↗

DOE OSTI2015

Design Fabrication and Characterization of High Density Silicon Photonic Components

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve e ciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satis ed by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which e cient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling on a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modi ed racetrack resonator is then presented enabling extraction of insertion loss data for highly e cient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.

36 MATERIALS SCIENCE↗

DOE OSTI2015

Failure detection in high-performance clusters and computers using chaotic map computations

A programmable media includes a processing unit capable of independent operation in a machine that is capable of executing 10.sup.18 floating point operations per second. The processing unit is in communication with a memory element and an interconnect that couples computing nodes. The programmable media includes a logical unit configured to execute arithmetic functions, comparative functions, and/or logical functions. The processing unit is configured to detect computing component failures, memory element failures and/or interconnect failures by executing programming threads that generate one or more chaotic map trajectories. The central processing unit or graphical processing unit is configured to detect a computing component failure, memory element failure and/or an interconnect failure through an automated comparison of signal trajectories generated by the chaotic maps.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

42 ENGINEERING↗

DOE OSTI2016

Modeling the Value of Integrated Canadian and U.S. Power Sector Expansion

The United States and Canada power systems are not isolated. Cross-border transmission and coordination of system operation create an interconnected power system, which results in combined imports and exports of electricity of greater than 70 TWh per year [1]. Currently, over 5 GW of new international transmission lines are in various stages of permitting and development. These lines may enable greater integration and coordination of the U.S. and Canada systems, which can in turn reduce challenges associated with integration of high penetrations of variable renewables. Furthermore, low-cost Canadian resources, such as wind and hydro, could contribute to compliance with the EPA's recently released Clean Power Plan. Improving integration and coordination internationally will reduce the costs of accessing these resources. This analysis work build on previous work by Ibanez and Zinaman [2]. In this work we seek to better understand the value of additional interconnection between the U.S. and Canadian power systems. Specifically, we quantify the value of additional interconnection and coordination within the Canadian-US integrated power system under scenarios in which large reductions (>80%) in power sector CO2 emissions are achieved. We explore how the ability to add additional cross-border transmission impacts capacity investment, the generation mix, system costs, and the ability of the system to integrate variable renewable energy into the power system. This analysis uses the Regional Energy Deployment System (ReEDS) capacity expansion model [3], [4] to quantify the value of the integrated power system expansion of the United States and Canada. ReEDS is an optimization model that assesses the deployment and operation (including transmission) of the electricity sector of the contiguous United States and Canadian provinces from 2016 through 2050. It has the ability to model the integration of renewable energy technologies into the grid. ReEDS captures renewable energy resources through the use of 356 individual resource regions and 134 balancing areas across the U.S. and is able to handle renewable energy issues such as variability in wind and solar output, transmission costs and constraints, and ancillary services requirements.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗

DOE OSTI2017

Fast Determination of Distribution-Connected PV Impacts Using a Variable Time-Step Quasi-Static Time-Series Approach: Preprint

The increasing deployment of distribution-connected photovoltaic (DPV) systems requires utilities to complete complex interconnection studies. Relatively simple interconnection study methods worked well for low penetrations of photovoltaic systems, but more complicated quasi-static time-series (QSTS) analysis is required to make better interconnection decisions as DPV penetration levels increase. Tools and methods must be developed to support this. This paper presents a variable-time-step solver for QSTS analysis that significantly shortens the computational time and effort to complete a detailed analysis of the operation of a distribution circuit with many DPV systems. Specifically, it demonstrates that the proposed variable-time-step solver can reduce the required computational time by as much as 84% without introducing any important errors to metrics, such as the highest and lowest voltage occurring on the feeder, number of voltage regulator tap operations, and total amount of losses realized in the distribution circuit during a 1-yr period. Further improvement in computational speed is possible with the introduction of only modest errors in these metrics, such as a 91 percent reduction with less than 5 percent error when predicting voltage regulator operations.

14 SOLAR ENERGY↗

DOE OSTI2018

Near-memory data reorganization engine

A memory subsystem package is provided that has processing logic for data reorganization within the memory subsystem package. The processing logic is adapted to reorganize data stored within the memory subsystem package. In some embodiments, the memory subsystem package includes memory units, a memory interconnect, and a data reorganization engine ("DRE"). The data reorganization engine includes a stream interconnect and DRE units including a control processor and a load-store unit. The control processor is adapted to execute instructions to control a data reorganization. The load-store unit is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and storing data to a store memory address of a memory unit.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Collective network for computer structures

A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Blumrich, Matthias A.↗

DOE OSTI2018

Spasers to speed up CMOS processors

A processor includes a transistor pair of a first transistor and a second transistor. The first transistor of the transistor pair is coupled to a Spaser and configured to output a drive current to the Spaser to pump the Spaser. Responsive to the drive current, the Spaser outputs surface plasmon polaritons (SPPs) which are fed to a plasmonic interconnect wire. The plasmonic interconnect wire propagates the SPPs. Further, the SPPs propagated on the plasmonic interconnect wire are detected by a phototransistor. Responsive to detecting the SPPs, the phototransistor generates an output current that is fed to a gate terminal of the second transistor to charge the second transistor.

42 ENGINEERING↗

DOE OSTI2019

Hybrid Systems to Enable High Penetration PV

A model for PV plus energy storage and fuel cells was developed in the System Advisor Model (SAM). This model was used to evaluate the ramp rate and interconnection capacity factor for a hypothetical utility-scale plant for several configuration options. For PV only, the plant experienced 3345 violations of a 10%/minute ramp up limitation and a interconnection capacity factor of 17.6%. Adding a battery reduced the violations to 154 per year and the magnitude of the average violation to 2%. Adding a fuel cell to the PV system increased the capacity factor to 78% without improving ramp violations. Using a combined PV plus storage plus fuel cell arrangement maintained the improved capacity factor while reducing ramp up violations to 23, illustrating the potential to operate a hybrid system both to enable grid integration requirements and increase utilization of the interconnection.

14 SOLAR ENERGY↗

DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗