Search NASA⌕ Search

SEARCH · Search NASA

Results for “capacitance”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 1,009 records · Page 56
All sourcesNASA NTRSDOE OSTI
NASA NTRS2013

SparkJet Efficiency

A novel method for determining the thermal efficiency of the SparkJet is proposed. A SparkJet is attached to the end of a pendulum. The motion of the pendulum subsequent to a single spark discharge is measured using a laser displacement sensor. The measured displacement vs time is compared with the predictions of a theoretical perfect gas model to estimate the fraction of the spark discharge energy which results in heating the gas (i.e., increasing the translational-rotational temperature). The results from multiple runs for different capacitances of c = 3, 5, 10, 20, and 40 micro-F show that the thermal efficiency decreases with higher capacitive discharges.

Golbabaei-Asl, Mona↗
NASA NTRS2013

Packaging Technologies for 500C SiC Electronics and Sensors

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Chen, Liang-Yu↗
NASA NTRS2013

Bulk Moisture and Salinity Sensor

Measurement and feedback control of nutrient solutions in plant root zones is critical to the development of healthy plants in both terrestrial and reduced-gravity environments. In addition to the water content, the amount of fertilizer in the nutrient solution is important to plant health. This typically requires a separate set of sensors to accomplish. A combination bulk moisture and salinity sensor has been designed, built, and tested with different nutrient solutions in several substrates. The substrates include glass beads, a clay-like substrate, and a nutrient-enriched substrate with the presence of plant roots. By measuring two key parameters, the sensor is able to monitor both the volumetric water content and salinity of the nutrient solution in bulk media. Many commercially available moisture sensors are point sensors, making localized measurements over a small volume at the point of insertion. Consequently, they are more prone to suffer from interferences with air bubbles, contact area of media, and root growth. This makes it difficult to get an accurate representation of true moisture content and distribution in the bulk media. Additionally, a network of point sensors is required, increasing the cabling, data acquisition, and calibration requirements. measure the dielectric properties of a material in the annular space of the vessel. Because the pore water in the media often has high salinity, a method to measure the media moisture content and salinity simultaneously was devised. Characterization of the frequency response for capacitance and conductance across the electrodes was completed for 2-mm glass bead media, 1- to 2-mm Turface (a clay like media), and 1- to 2-mm fertilized Turface with the presence of root mass. These measurements were then used to find empirical relationships among capacitance (C), the dissipation factor (D), the volumetric water content, and the pore water salinity.

Nurge, Mark↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗
NASA NTRS2013

Aligned Carbon Nanotube Tape for Sensor Applications

For this effort, will concentrate on three applications: Vibration Gyroscope utilizes piezoelectric properties of the tape and Coriolis effect Accelerometer utilizes the piezoresistive property Strain Gauge utilizes piezoresistive property Accelerometer and Strain Gauge can also utilize piezoelectric effect Test piezoelectric properties using facilities at the Microfabrication Laboratory (AMRDEC) . Enhance piezoelectric effect using polyvinylidine fluoride and P(VDF ]TrFE) which is readily polarizable .Spray matrix solution while winding fiber; Sandwich of CNT tape and PVDF film (DOE .Two Level) . Construct and test prototype vibration gyroscope . Construct and test prototype accelerometer using cantilever design . Test strain sensitivity of CNT tape against industrial strain gauge . Embed CNT tape in composite samples as well as on surface and test to failure (4 ]point bend) A piezoelectric device exhibits an electrical response from a mechanical applied stress. . A piezoelectric device has both capacitance and resistance properties in which by applying an electric field from a waveform will exert a mechanical stress that can be monitored for a response. . The typical waveform applied is a sinusoidal waveform of a defined voltage for a defined period. The defined voltage is driven from 0 volts to the positive defined volts then back to 0 and driven to negative defined volts then back to 0. . Example. Vmax set to 10V and period set to 10 ms. . Voltage will start at zero, go to 10 volts, return to zero, go to ]10 volts and return to zero during 10 ms. . Applying this electrical field to a DUT, the capacitance response and resistance response can be observed. CNT tape is easier to manufacture and cheaper than micromachining silicon or other ceramic piezoelectric used in gyroscopes and accelerometers CNT tape properties can be modified during manufacture for specific application CNT tape has enhanced mechanical and thermal properties in addition to unique electrical properties CNT tape as a strain gauge in Structural Health Monitoring will provide an excellent material to embed within composite structures

Tucker, Dennis S.↗
NASA NTRS2013

Efficiency of SparkJet

The thermal efficiency of a SparkJet is evaluated by measuring the impulse response of a pendulum subject to a single spark discharge. The SparkJet is attached to the end of a pendulum. A laser displacement sensor is used to measure the displacement of the pendulum upon discharge. The pendulum motion is a function of the fraction of the discharge energy that is channeled into the heating of the gas (i.e., increasing the translational-rotational temperature). A theoretical perfect gas model is used to estimate the portion of the energy from the heated gas that results in equivalent pendulum displacement as in the experiment. The earlier results from multiple runs for different capacitances of C = 3, 5, 10, 20, and 40(micro)F demonstrate that the thermal efficiency decreases with higher capacitive discharges.1 In the current paper, results from additional run cases have been included and confirm the previous results

Golbabaei-Asl, M.↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗
NASA NTRS2013

Mapping Electrical Crosstalk in Pixelated Sensor Arrays

The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

Seshadri, Suresh↗
NASA NTRS2014

Computationally Efficient Modeling and Simulation of Large Scale Systems

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Jain, Jitesh↗
NASA NTRS1997

Solid-state Image Sensor with Focal-plane Digital Photon-counting Pixel Array

A solid-state focal-plane imaging system comprises an NxN array of high gain. low-noise unit cells. each unit cell being connected to a different one of photovoltaic detector diodes, one for each unit cell, interspersed in the array for ultra low level image detection and a plurality of digital counters coupled to the outputs of the unit cell by a multiplexer(either a separate counter for each unit cell or a row of N of counters time shared with N rows of digital counters). Each unit cell includes two self-biasing cascode amplifiers in cascade for a high charge-to-voltage conversion gain (greater than 1mV/e(-)) and an electronic switch to reset input capacitance to a reference potential in order to be able to discriminate detection of an incident photon by the photoelectron (e(-))generated in the detector diode at the input of the first cascode amplifier in order to count incident photons individually in a digital counter connected to the output of the second cascade amplifier. Reseting the input capacitance and initiating self-biasing of the amplifiers occurs every clock cycle of an integratng period to enable ultralow light level image detection by the may of photovoltaic detector diodes under such ultralow light level conditions that the photon flux will statistically provide only a single photon at a time incident on anyone detector diode during any clock cycle.

Fossum, Eric R.↗
NASA NTRS2016

Li-Doped Ionic Liquid Electrolytes: From Bulk Phase to Interfacial Behavior

Ionic liquids have been proposed as candidate electrolytes for high-energy density, rechargeable batteries. We present an extensive computational analysis supported by experimental comparisons of the bulk and interfacial properties of a representative set of these electrolytes as a function of Li-salt doping. We begin by investigating the bulk electrolyte using quantum chemistry and ab initio molecular dynamics to elucidate the solvation structure of Li(+). MD simulations using the polarizable force field of Borodin and coworkers were then performed, from which we obtain an array of thermodynamic and transport properties. Excellent agreement is found with experiments for diffusion, ionic conductivity, and viscosity. Combining MD simulations with electronic structure computations, we computed the electrochemical window of the electrolytes across a range of Li(+)-doping levels and comment on the role of the liquid environment. Finally, we performed a suite of simulations of these Li-doped electrolytes at ideal electrified interfaces to evaluate the differential capacitance and the equilibrium Li(+) distribution in the double layer. The magnitude of differential capacitance is in good agreement with our experiments and exhibits the characteristic camel-shaped profile. In addition, the simulations reveal Li(+) to be highly localized to the second molecular layer of the double layer, which is supported by additional computations that find this layer to be a free energy minimum with respect to Li(+) translation.

molecular dynamics↗
NASA NTRS2016

Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.

dielectric performance↗
NASA NTRS2017

Mapping Electrical Crosstalk in Pixelated Sensor Arrays

The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

Seshadri, Suresh↗
NASA NTRS2011

Design and Development of 256x256 Linear Mode Low-Noise Avalanche Photodiode Arrays

A larger format photodiode array is always desirable for many LADAR imaging applications. However, as the array format increases, the laser power or the lens aperture has to increase to maintain the same flux per pixel thus increasing the size, weight and power of the imaging system. In order to avoid this negative impact, it is essential to improve the pixel sensitivity. The sensitivity of a short wavelength infrared linear-mode avalanche photodiode (APD) is a delicate balance of quantum efficiency, usable gain, excess noise factor, capacitance, and dark current of APD as well as the input equivalent noise of the amplifier. By using InA1As as a multiplication layer in an InP-based APD, the ionization coefficient ratio, k, is reduced from 0.40 (lnP) to 0.22, and the excess noise is reduced by about 50%. An additional improvement in excess noise of 25% was achieved by employing an impact-ionization-engineering structure with a k value of 0.15. Compared with the traditional InP structure, about 30% reduction in the noise-equivalent power with the following amplifier can be achieved. Spectrolab demonstrated 30-um mesa APD pixels with a dark current less than 10 nA and a capacitance of 60 fF at gain of 10. APD gain uninformity determines the usable gain of most pixels in an array, which is critical to focal plane array sensitivity. By fine tuning the material growth and device process, a break-down-voltage standard deviation of 0.1 V and gain of 30 on individual pixels were demonstrated in our 256x256 linear-mode APD arrays.

Yuan, Ping↗
NASA NTRS2019

An Analytic Model for Estimating the First Contact Resistance Needed to Avoid Damaging ESD During Spacecraft Docking in GEO

NASA’s Gateway program will involve spacecraft (s/c) docking in the outer radiation belt in order to transfer Gateway elements between s/c for transport to lunar orbit. The charging of these s/c to different potentials prior to docking raises the possibility of a damaging electrostatic discharge (ESD) at the time of first contact between the s/c. A proposed mitigation strategy is for first contact to occur prior to docking through a resistor with resistance R that would lower the potential difference at an optimal rate to a sufficiently low value to prevent ESD damage. The coupling of s/c by a resistor can be modeled by SPIS, but for realistic two s/c models SPIS can take hours to simulate the evolution of the s/c surface charges and potentials to an equilibrium state. Our objective is to develop a simpler model of s/c resistive coupling that runs orders of magnitude faster while providing useful first design estimates of the time variation of the s/c potentials, current through the resistor, and how these vary with R and s/c configuration This configuration is defined by the relative separation and orientation of the s/c, and their solar illumination. The configuration and geometry of the s/c determine their capacitive coupling. The s/c capacitances are computed using Nascap-2K. This poster presents the first version of such a model, and initial tests.

Goodman, Michael L.↗
NASA NTRS2019

An Analytic Model for Estimating the First Contact Resistance Needed to Avoid Damaging ESD During Spacecraft Docking in GEO

NASA’s Gateway program is to involve spacecraft (s/c) docking in the outer radiation belt in order to transfer Gateway elements between s/c for transport to lunar orbit. The charging of these s/c to different potentials prior to docking raises the possibility of a damaging electrostatic discharge (ESD) at the time of first contact between the s/c. A proposed mitigation strategy is for first contact to occur prior to docking through a resistor with resistance R that would lower the potential difference at an optimal rate to a sufficiently low value to prevent a damaging ESD. The coupling of s/c by a resistor can be modeled by SPIS (Spacecraft Plasma Interaction System), but for realistic two s/c models SPIS can take hours to simulate the evolution of the s/c surface charges and potentials to an equilibrium state. Our objective is to develop a simpler model of s/c resistive coupling that runs orders of magnitude faster while providing useful first design estimates of the time variation of the s/c potentials, current through the resistor, and how these vary with R and s/c configuration. This configuration is defined by the relative separation and orientation of the s/c, and their solar illumination. The configuration and geometry of the s/c determine their capacitive coupling. The s/c capacitances are computed using Nascap-2K. This abstract and the associated poster describe the first version of such a model, and initial tests.

Goodman, Michael L.↗
NASA NTRS2019

Modeling and Mitigation of Multi-Loops Related Device Overvoltage in Three Level Active Neutral Point Clamped Converter

This paper establishes an analytical model for the device drain-source overvoltage related to the two loops in three level active neutral point clamped (3L-ANPC) converters. Taking into account the non-linear device output capacitance, two commonly used modulations are investigated in detail. The result shows that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the non-active clamping switch off, the effect of the non-linear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in PCB and busbar design. A 500 kVA 3L-ANPC converter using SiC MOSFETs is built and tested. The experimental results validate the overvoltage model of the two modulations as well as the busbar design. With the non-active clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

Model↗
NASA NTRS2021

Effect of High Temperature Storage on AC Characteristics of Polymer Tantalum Capacitors

Replacement of MnO2 with conductive polymers as cathode materials in chip tantalum capacitors allows for a substantial reduction of the equivalent series resistance (ESR), improvement of frequency characteristics, and elimination of the possibility of ignition during failures. One of the drawbacks of chip polymer tantalum capacitors (CPTCs) is a relatively poor long-term stability at high temperatures. In this work, variations of capacitance, dissipation factor, and ESR in different types of capacitors including automotive grade parts from three manufacturers have been monitored during storage at temperatures from 100 ºC to 175 ºC for up to 18,000 hours. Results show that ESR is the most and capacitance the least sensitive to degradation parameter. Times to parametric failures have been simulated using a Weibull-Arrhenius model that allowed for assessments of activation energies of the degradation and prediction of times to failure at the use temperature. Degradation of CPTCs was explained by thermo-oxidative processes in conductive polymers that result in exponential increasing of the resistivity with time of ageing. This process starts after a certain incubation period that depends on packaging materials and design and corresponds to the time that is necessary to form delamination between the encapsulating molding compound and lead frame. The effectiveness of the existing qualification procedures to assure stable operation of CPTCs is discussed.

Alexander A Teverovsky↗