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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,063 records · Page 59
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Scanning Electron Microscope Mapping System Developed for Detecting Surface Defects in Fatigue Specimens

An automated two-degree-of-freedom specimen positioning stage has been developed at the NASA Glenn Research Center to map and monitor defects in fatigue specimens. This system expedites the examination of the entire gauge section of fatigue specimens so that defects can be found using scanning electron microscopy (SEM). Translation and rotation stages are driven by microprocessor-based controllers that are, in turn, interfaced to a computer running custom-designed software. This system is currently being used to find and record the location of ceramic inclusions in powder metallurgy materials. The mapped inclusions are periodically examined during interrupted fatigue experiments. The number of cycles to initiate cracks from these inclusions and the rate of growth of initiated cracks can then be quantified. This information is necessary to quantify the effect of this type of defect on the durability of powder metallurgy materials. This system was developed with support of the Ultra Safe program.

Bonacuse, Peter J.↗
NASA NTRS2005

Reconfigurable Processing Module

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

Somervill, Kevin↗
NASA NTRS2005

Virtex-II Pro PowerPC SEE Characterization Test Methods and Results

The Xilinx Vix-11 Pro is a platform FPGA that embeds multiple microprocessors within the fabric of an SRAM-based reprogrammable FPGA. The variety and quantity of resources provided by this family of devices make them very attractive for spaceflight applications. However,these devices will be susceptible to single event effects (SEE), which must be mitigated. Observations from prior testing of the Xilinx Virtex-II Pro suggest that the PowerPC core has significant vulnerability to SEES. However, these initial tests were not designed to exclusively target the functionality of the PowerPC, therefore making it difficult to distinguish processor upsets from fabric upsets. The main focus of this paper involves detailed SEE testing of the embedded PowerPC core. Due to the complexity of the PowerPC, various custom test applications, both static and dynamic, will be designed to isolate each Unit of the processor. Collective analysis of the test results will provide insight into the exact upset mechanism of the PowerPC. With this information, mitigations schemes can be developed and tested that address the specific susceptibilities of these devices. The test bed will be the Xilinx SEE Consortium Virtex-II Pro test board, which allows for configuration scrubbing, design triplication, and ease of data collection. Testing will be performed at the Indiana University Cyclotron Facility using protons of varying energy levels and fluencies. This paper will present the detailed test approach along with the results.

Petrick, David↗
NASA NTRS2005

Physical Intelligent Sensors

This paper proposes the development of intelligent sensors as part of an integrated systems approach, i.e. one treats the sensors as a complete system with its own sensing hardware (the traditional sensor), A/D converters, processing and storage capabilities, software drivers, self-assessment algorithms, communication protocols and evolutionary methodologies that allow them to get better with time. Under a project being undertaken at the NASA s Stennis Space Center, an integrated framework is being developed for the intelligent monitoring of smart elements. These smart elements can be sensors, actuators or other devices. The immediate application is the monitoring of the rocket test stands, but the technology should be generally applicable to the Integrated Systems Health Monitoring (ISHM) vision. This paper outlines progress made in the development of intelligent sensors by describing the work done till date on Physical Intelligent Sensors (PIS). The PIS discussed here consists of a thermocouple used to read temperature in an analog form which is then converted into digital values. A microprocessor collects the sensor readings and runs numerous embedded event detection routines on the collected data and if any event is detected, it is reported, stored and sent to a remote system through an Ethernet connection. Hence the output of the PIS is data coupled with confidence factor in the reliability of the data which leads to information on the health of the sensor at all times. All protocols are consistent with IEEE 1451.X standards. This work lays the foundation for the next generation of smart devices that have embedded intelligence for distributed decision making capabilities.

Bandhil, Pavan↗
NASA NTRS1997

An Assessment of a Beowulf System for a Wide Class of Analysis and Design Software

A typical Beowulf system, such as the machine at the Jet Propulsion Laboratory (JPL), may comprise 16 nodes interconnected by 100 base T Fast Ethernet. Each node may include a single Inter Pentium Pro 200 MHz microprocessor, 128 MBytes of DRAM, 2.5 GBytes of IDE disk, and PCI bus backplane, and an assortment of other devices.

Beowulf System↗
NASA NTRS1997

(abstract) Realization of a Faster, Cheaper, Better Mission and Its New Paradigm Star Tracker, the Advanced Stellar Compass

The first Danish satellite, rsted, will be launched in August of 1997. The scientific objective of sted is to perform a precision mapping of the Earth's magnetic field. Attitude data for the payload and the satellite are provided by the Advanced Stellar Compass (ASC) star tracker. The ASC consists of a CCD star camera and a capable microprocessor which operates by comparing the star image frames taken by the camera to its internal star catalogs.

ASC Advanced Stellar Compass Denmark CCD star cata↗
NASA NTRS2006

Valve Health Monitoring System Utilizing Smart Instrumentation

The valve monitoring system is a stand alone unit with network capabilities for integration into a higher level health management system. The system is designed for aiding in failure predictions of high-geared ball valves and linearly actuated valves. It performs data tracking and archiving for identifying degraded performance. The data collection types are cryogenic cycles, total cycles, inlet temperature, body temperature torsional strain, linear bonnet strain, preload position, total travel and total directional changes. Events are recorded and time stamped in accordance with the IRIG B True Time. The monitoring system is designed for use in a Class 1 Division II explosive environment. The basic configuration consists of several instrumentation sensor units and a base station. The sensor units are self contained microprocessor controlled and remotely mountable in three by three by two inches. Each unit is potted in a fire retardant substance without any cavities and limited to low operating power for maintaining safe operation in a hydrogen environment. The units are temperature monitored to safeguard against operation outside temperature limitations. Each contains 902-928 MHz band digital transmitters which meet Federal Communication Commission's requirements and are limited to a 35 foot transmission radius for preserving data security. The base-station controller correlates data from the sensor units and generates data event logs on a compact flash memory module for database uploading. The entries are also broadcast over an Ethernet network. Nitrogen purged National Electrical Manufactures Association (NEMA) Class 4 enclosures are used to house the base-station

Jensen, Scott L.↗
NASA NTRS2007

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗
NASA NTRS2006

Incident Involving 30-Ah Li-ion Cell at NASA Glenn Research Center

The key lesson learned from the February 17, 2006 cell explosion incident is that PC-based test-systems, even those having built-in watchdog monitors, can lose control and malfunction. In the case of lithiumion cell/battery testing, the stored energy can be released explosively causing considerable injury and damage to facilities. The investigation showed that although the Arbin system has a built-in watchdog monitor, the circumstances of the incident defeated the action of the watchdog and allowed the cycler to continue operation without control. An upgrade to the most recent version of Arbin software (version 4) was provided as a fix to the presumed control problem. This upgrade included newer EPROM s for the cycler microprocessor. Investigation revealed that similar incidents have occurred at other NASA centers with a variety of PC-based test instruments. JPL suffered an incident with Maccor testers and the GRC fuel cell group observed similar problems with LabView software. This is not exclusively an Arbin problem, but an issue with all PC-based systems. In this incident, it was fortunate that the event occurred after-hours with no-one in the room. The facility arrangement placed control consoles adjacent to the test chamber doors. Had someone been in the room during the event, they would have been exposed to hot debris and toxic combustion products. It was also fortunate that the exploded cell stayed inside the chamber after the door was forced open. If the cell had been ejected into the room it could have caused serious facility damage by impact and possibly caused a fire in the facility.

Bennett, William↗
NASA NTRS2007

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS2007

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS1988

Method and apparatus for implementing a maximum-likelihood decoder in a hypercube network

A method and a structure to implement maximum-likelihood decoding of convolutional codes on a network of microprocessors interconnected as an n-dimensional cube (hypercube). By proper reordering of states in the decoder, only communication between adjacent processors is required. Faster and more efficient operation is enabled, and decoding of large constraint length codes is feasible using standard VLSI technology.

Pollara-Bozzola, Fabrizio↗
NASA NTRS1999

Portable flash lamp reflectance analyzer system and method

The system and method allow spectroscopic analysis of vegetation or the like without effects from changing sun and cloud conditions, undesired portions of the area of interest or atmospheric disturbances. The system (1) includes a light source (5) such as a xenon flash lamp, a telescope (7), a spectrometer (9), an analog/digital converter (11), a memory (13), a display (15), and an on-board microprocessor (17) or a port (19) for attachment to a laptop computer. The system is taken to an area of interest in the woods (step 41), the vegetation is illuminated from below (step 43) and data are taken (step 45).

Kalshoven, James Edward↗
NASA NTRS1985

Pulse width modulation inverter with battery charger

An inverter is connected between a source of DC power and a three-phase AC induction motor, and a microprocessor-based circuit controls the inverter using pulse width modulation techniques. In the disclosed method of pulse width modulation, both edges of each pulse of a carrier pulse train are equally modulated by a time proportional to sin .theta., where .theta. is the angular displacement of the pulse center at the motor stator frequency from a fixed reference point on the carrier waveform. The carrier waveform frequency is a multiple of the motor stator frequency. The modulated pulse train is then applied to each of the motor phase inputs with respective phase shifts of 120.degree. at the stator frequency. Switching control commands for electronic switches in the inverter are stored in a random access memory (RAM) and the locations of the RAM are successively read out in a cyclic manner, each bit of a given RAM location controlling a respective phase input of the motor. The DC power source preferably comprises rechargeable batteries and all but one of the electronic switches in the inverter can be disabled, the remaining electronic switch being part of a flyback DC-DC converter circuit for recharging the battery.

Slicker, James M.↗
NASA NTRS1987

Brushless DC motor control system responsive to control signals generated by a computer or the like

A control system for a brushless DC motor responsive to digital control signals is disclosed. The motor includes a multiphase wound stator and a permanent magnet rotor. The rotor is arranged so that each phase winding, when energized from a DC source, will drive the rotor through a predetermined angular position or step. A commutation signal generator responsive to the shaft position provides a commutation signal for each winding. A programmable control signal generator such as a computer or microprocessor produces individual digital control signals for each phase winding. The control signals and commutation signals associated with each winding are applied to an AND gate for that phase winding. Each gate controls a switch connected in series with the associated phase winding and the DC source so that each phase winding is energized only when the commutation signal and the control signal associated with that phase winding are present. The motor shaft may be advanced one step at a time to a desired position by applying a predetermined number of control signals in the proper sequence to the AND gates and the torque generated by the motor may be regulated by applying a separate control signal to each AND gate which is pulse width modulated to control the total time that each switch connects its associated winding to the DC source during each commutation period.

Packard, Douglas T.↗