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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

A first look at AS-ROC: a Si-Ge integrated chip readout for fast timing

Abstract Advances in timing detector technology require new specialized readout electronics. Applications demand below 10 ps time of arrival resolution and low power for a low repetition rate. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc., in collaboration with UC Santa Cruz, has developed a prototype SiGe front-end readout chip optimized for low power and timing resolution. Two versions of the chip were produced with performance in simulation: a more power version with 10 ps resolution at 5 fC with 1.1 mW/channel, and a less power version with 10 ps resolution at 8 fC with 0.6 mW/channel.The chip was produced at Tower Semiconductor with 350 nm technology. The ASIC from the prototype run shows good performance: a rise time of 0.7–1 ns and 25 mV per fC response with RMS noise <1 mV. Simulation and results from the prototype will be reported in this paper.

Instruments & Instrumentation↗
DOE OSTI2022

Distributed Quantum Error Correction for Chip-Level Catastrophic Errors

Quantum error correction holds the key to scaling up quantum computers. Cosmic ray events severely impact the operation of a quantum computer by causing chip-level catastrophic errors, essentially erasing the information encoded in a chip. Here, in this work, we present a distributed error correction scheme to combat the devastating effect of such events by introducing an additional layer of quantum erasure error correcting code across separate chips. We show that our scheme is fault tolerant against chip-level catastrophic errors and discuss its experimental implementation using superconducting qubits with microwave links. Our analysis shows that in state-of-the-art experiments, it is possible to suppress the rate of these errors from 1 per 10 s to less than 1 per month.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Hardware-in-the-Loop Evaluation of Grid-Edge DER Chip Integration Into Next-Generation Smart Meters

To facilitate the implementation of distributed energy resource management systems (DERMS), we propose to insert a grid-edge distributed energy resource (DER) chip hosting a DERMS algorithm into the next generation of smart meters. This will create a pathway for the wide adoption of DERMS technology because many utilities plan to invest in advanced metering infrastructure in the near future. This will also bridge the gap between an electrical power utility and DERs behind the meter. The DER chip is designed to follow power direction signals from the DERMS coordinator while balancing its local objectives. We tested the chip using a controller- and power-hardware-in-the-loop evaluation under three scenarios that a DERMS could face in the real world. The DER chip was capable of and effective at directing four heterogeneous DERs to respond to a DERMS coordinator for grid services (e.g., voltage regulation and a virtual power plant).

distributed energy resource management system↗
DOE OSTI2020

Ultrahigh areal number density solid-state on-chip microsupercapacitors via electrohydrodynamic jet printing

Microsupercapacitors (MSCs) have garnered considerable attention as a promising power source for microelectronics and miniaturized portable/wearable devices. However, their practical application has been hindered by the manufacturing complexity and dimensional limits. Here, we develop a new class of ultrahigh areal number density solid-state MSCs (UHD SS–MSCs) on a chip via electrohydrodynamic (EHD) jet printing. This is, to the best of our knowledge, the first study to exploit EHD jet printing in the MSCs. The activated carbon-based electrode inks are EHD jet-printed, creating interdigitated electrodes with fine feature sizes. Subsequently, a drying-free, ultraviolet-cured solid-state gel electrolyte is introduced to ensure electrochemical isolation between the SS–MSCs, enabling dense SS–MSC integration with on-demand (in-series/in-parallel) cell connection on a chip. The resulting on-chip UHD SS–MSCs exhibit exceptional areal number density [36 unit cells integrated on a chip (area = 8.0 mm x 8.2 mm), 54.9 cells cm -2 ] and areal operating voltage (65.9 V cm -2 ).

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

Prospects and applications of on-chip lasers

Abstract Integrated silicon photonics has sparked a significant ramp-up of investment in both academia and industry as a scalable, power-efficient, and eco-friendly solution. At the heart of this platform is the light source, which in itself, has been the focus of research and development extensively. This paper sheds light and conveys our perspective on the current state-of-the-art in different aspects of application-driven on-chip silicon lasers. We tackle this from two perspectives: device-level and system-wide points of view. In the former, the different routes taken in integrating on-chip lasers are explored from different material systems to the chosen integration methodologies. Then, the discussion focus is shifted towards system-wide applications that show great prospects in incorporating photonic integrated circuits (PIC) with on-chip lasers and active devices, namely, optical communications and interconnects, optical phased array-based LiDAR, sensors for chemical and biological analysis, integrated quantum technologies, and finally, optical computing. By leveraging the myriad inherent attractive features of integrated silicon photonics, this paper aims to inspire further development in incorporating PICs with on-chip lasers in, but not limited to, these applications for substantial performance gains, green solutions, and mass production.

Zhou, Zhican↗
DOE OSTI2020

Silicon photonic chip for 16-channel wavelength division (de-)multiplexing in the O-band

We experimentally demonstrate a silicon photonic chip-scale 16-channel wavelength division multiplexer (WDM) operating in the O-band. The silicon photonic chip consists of a common-input bus waveguide integrated with a sequence of 16 spectral add-drop filters implemented by 4-port contra-directional Bragg couplers and resonant cladding modulated perturbations. The combination of these features reduces the spectral bandwidth of the filters and improves the crosstalk. An apodization of the cladding modulated perturbations between the bus and the add/drop waveguides is used to optimize the strength of the coupling coefficient in the propagation direction to reduce the intra-channel crosstalk on adjacent channels. The fabricated chip was validated experimentally with a measured intra-channel crosstalk of ∼−18.9 dB for a channel spacing of 2.6 nm. The multiplexer/demultiplexer chip was also experimentally tested with a 10 Gbps data waveform. The resulting eye-pattern indicates that this approach is suitable for datacenter WDM-based interconnects in the O-band with large aggregate bandwidths.

Davis, Jordan A. (ORCID:0000000343483295)↗
DOE OSTI2021

On-chip optical tweezers based on freeform optics

Since its advent in the 1970s, optical tweezers have been widely deployed as a preferred non-contact technique for manipulating microscale objects. On-chip integrated optical tweezers, which afford significant size, weight, and cost benefits, have been implemented, relying upon near-field evanescent waves. As a result, these tweezers are only capable of manipulation in near-surface regions and often demand high power since the evanescent interactions are relatively weak. We introduce on-chip optical tweezers based on freeform micro-optics, which comprise optical reflectors or refractive lenses integrated on waveguide end facets via two-photon polymerization. The freeform optical design offers unprecedented degrees of freedom to design optical fields with strong three-dimensional intensity gradients, useful for trapping and manipulating suspended particles in an integrated chip-scale platform. We demonstrate the design, fabrication, and measurement of both reflective and refractive micro-optical tweezers. The reflective tweezers feature a remarkably low trapping threshold power, and the refractive tweezers are particularly useful for multiparticle trapping and interparticle interaction analysis. Our integrated micro-optical tweezers uniquely combine a compact footprint, broadband operation, high trapping efficiency, and scalable integration with planar photonic circuits. This class of tweezers is promising for on-chip sensing, cell assembly, particle dynamics analysis, and ion trapping.

Yu, Shaoliang (ORCID:000000026072425X)↗
DOE OSTI2023

Status of CHIP-TRAP: The Central Michigan University High-Precision Penning Trap

Precise and accurate atomic mass data provide crucial information for applications in a wide range of fields in physics and beyond, including astrophysics, nuclear structure, particle and neutrino physics, fundamental symmetries, chemistry, and metrology. The most precise atomic mass measurements are performed on charged particles confined in a Penning trap. Here, we describe the development, status, and outlook of CHIP-TRAP: the Central Michigan University high-precision Penning trap. CHIP-TRAP aims to perform ultra-high precision (~1 part in 10 11 fractional precision) mass measurements on stable and long-lived isotopes produced with external ion sources and transported to the Penning traps. Along the way, ions of a particular m/q are selected with a multi-reflection time-of-flight mass separator (MR-TOF-MS), with further filtering performed in a cylindrical capture trap before the ions are transported to a pair of hyperbolic measurement traps. In this paper, we report on the design and status of CHIP-TRAP and present results from the commissioning of the ion sources, MR-TOF-MS, and capture trap. We also provide an outlook on the continued development and commissioning of CHIP-TRAP.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS1982

Exit chipping in ID sawing of silicon crystals

The processes involved in exit chipping which may occur in the internal diameter diamond sawing of silicon crystals were examined. An interpretation of chipping observations is given in terms of crack propagation as acted upon by the sawing stresses. Since the exit chips are roughly parallel to saw marks, the general locus of the crack must be determined by contact stresses although the exact locus depends on already existing subfractures located in the kerf region which are caused by more than one abrasive particle. The crack starts at either edge since these are weak areas in flexure. In the more extensive "saw fracture", the fracture plane often changes part-way across the slice to be other than parallel to the saw mark because the speed of the crack accelerates beyond the speed of the blade travel; i.e., outstrips the advance of the contact stress field. The influences of various external factors on the opening of the crack are divided into two types: factors that wedge the crack apart and those that bend the slice away from the crystal. From a consideration of these factors, conditions for minimizing exit chipping are defined.

Dyer, L. D.↗
NASA NTRS1982

Planar multijunction high voltage solar cell chip

A new innovative planar multijunction solar cell chip for concentrated sunlight applications is proposed. The chip consists of many voltage-generating regions, called unit cells, which are connected in series within a single silicon wafer, thereby providing a high open-circuit voltage at multiple sun illumination levels. The unit cells are fabricated on 75 micron thick p-type single crystal silicon substrate. Each chip consists of 1.42 x 9.63 mm n(+)/p collecting junctions on the back of the wafer, while the illuminated front surface area is divided into 0.3 micron deep n(+) regions. The fabrication sequence includes standard degreasing and cleaning procedures, double-sided alignment photomasking, introduction of boron and phosphorus impurities, and photolithography. The open circuit voltage of the chip increased rapidly with illumination up to about 4 AM1 suns, and then began to saturate at the sum of the individual unit cell voltages of 3.5 above 4 AM1 suns. A short circuit density per unit cell of 300 mA/sq cm at 20 AM1 suns was observed.

Valco, G. J.↗
NASA NTRS1984

Chip level modeling of LSI devices

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Armstrong, J. R.↗
NASA NTRS1987

VLSI-Chip Tester

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.↗
NASA NTRS1986

A system for the functional testing and simulation of custom and semicustom VLSI chips

A system for the functional testing and simulation of custom and semicustom very large scale integrated (VLSI) chips that are designed using the integrated UNIX-based computer-aided design (CAD) system is described. The testing and simulation system consists of two parts. One of these is a special purpose hardware device that is capable of controlling the digital imputs and outputs on a custom chip. This device, the Digital Microcircuit Functionality Tester (DMFT) system, can be operated by itself or in conjunction with the VAX host computer on the CAD system. The DMFT is integrated into a microprobe station so that these signals can be injected or read from nodes inside the chip, as well as at the pins. The second part of the system is a software package that is installed on the VAX. This software package, logic, includes a full-screen editor for developing chip test sequences and drivers for both the DMFT and the esim logic simulator.

Olson, E. M.↗
NASA NTRS1989

On testing VLSI chips for the big Viterbi decoder

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Hsu, I. S.↗
NASA NTRS1993

Cascaded VLSI Chips Help Neural Network To Learn

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Duong, Tuan A.↗
NASA NTRS1993

The role of simulation in the design of a neural network chip

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

Desai, Utpal↗
NASA NTRS1996

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Le, Binh Q.↗