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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [Fermilab]↗
DOE OSTI2026

Ultra-low thermal resistance and pressure drop copper and copper-tungsten diamond-shaped pin fin cold plates for liquid cooling of electronics

Modern and future data centers face increasing cooling challenges due to increasing chip thermal design power and die size, along with the need to reduce energy consumption used for cooling. High performance cooling solutions that maintain a low chip junction temperature are needed to ensure electronics reliability. This work develops an ultra-low thermal resistance and low pressure drop 75 mm × 75 mm cold plate, intended for next-generation electronics cooling. The cold plate features an array of diamond-shaped pin fins and integrated copper tungsten heat spreader, selected for its low coefficient of thermal expansion which reduces thermomechanical deformation and allows for closer integration of the cold plate with silicon dies. Starting with 300 candidate designs, three-dimensional computational fluid dynamics simulations predict the thermal-hydraulic performance of cold plate subsections. The highest performing geometries are evaluated with high fidelity simulations. Four cold plates are manufactured for experiments: three with diamond-shaped pin fins and one with straights fins for comparison purposes. The cold plates are fabricated from copper-tungsten (CuW), copper (Cu), or aluminum-silicon-magnesium alloy (AlSi10Mg). The diamond-shaped pin fins achieve a roughly 15 % lower thermal resistance compared to the conventional straight fin microchannel. The highest performing design achieves a chip-to-coolant (including thermal interface material) thermal resistance of 9.0 K/kW in CuW and 6.9 K/kW in Cu under a 1 kW heat load with an inlet-to-outlet pressure drop of 9.0 kPa and water as the working fluid. This work demonstrates ultra-low thermal resistance and pressure drop cold plates for large die, high heat load applications, and shows that CuW is an attractive cold plate material for improved reliability in next generation data center cooling.

Coefficient of thermal expansion↗
DOE OSTI2024

The Impact of Lithium Anode Interface on Capacity Fade in Polymer Electrolyte-Based Solid-State Batteries

This study investigates the Li stripping-plating morphology and failure mechanisms in full cells consisting of a solid polymer electrolyte (SPE) with two commercial Li anodes: Li chip and Li foil. The primary identified failure mechanism of the SPE cell is capacity fade, regardless of the Li manufacturer. While the cathode’s role in capacity fade is evident, the Li anode significantly influences cycling performance, with Li foil cells cycling 50% longer than Li chip cells, a statistical difference. Further, post-mortem scanning electron microscopy and X-ray photoelectron spectroscopy results attribute the Li chip’s faster capacity fade to a loss of contact and continuous growth of the solid electrolyte interphase (SEI). Conversely, Li foil maintains consistent contact with the solid polymer, displaying a thin and stable SEI. Additionally, failure mechanisms between a gel electrolyte in previous work and the dry SPE are compared.

25 ENERGY STORAGE↗
DOE OSTI2025

Bottom-up fabrication of 2D Rydberg exciton arrays in cuprous oxide

Solid-state platforms provide exceptional opportunities for advancing on-chip quantum technologies by enhancing interaction strengths through coupling, scalability, and robustness. Cuprous oxide (Cu 2 O) has recently emerged as a promising medium for scalable quantum technology due to its high-lying Rydberg excitonic states, akin to those in hydrogen atoms. To harness these nonlinearities for quantum applications, the confinement dimensions must match the Rydberg blockade size, which can reach several microns in Cu 2 O. Using a CMOS-compatible growth technique, this study demonstrates the bottom-up fabrication of site-selective arrays of Cu 2 O microparticles. We observed Rydberg excitons up to the principal quantum number n = 5 within these Cu 2 O arrays on a quartz substrate and analyzed the spatial variation of their spectrum across the array, showing robustness and reproducibility on a large chip. These results lay the groundwork for the deterministic growth of Cu 2 O around photonic structures, enabling substantial light-matter interaction on integrated photonic platforms and paving the way for scalable, on-chip quantum devices.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Mitigating cosmic-ray-like correlated events with a modular quantum processor

Quantum processors based on superconducting qubits are being scaled to larger qubit numbers, enabling the implementation of small-scale quantum error-correction codes. However, catastrophic chip-scale correlated errors have been observed in these processors, attributed to, e.g., cosmic ray impacts, which challenge conventional error-correction codes such as the surface code. These events are characterized by a temporary but pronounced suppression of the qubit-energy relaxation times. Here, in this study, we explore the potential for modular quantum computing architectures to mitigate such correlated energy decay events. We measure cosmic-ray-like events in a quantum processor comprising a motherboard and two flip-chip bonded daughterboard modules, each module containing two superconducting qubits. We monitor the appearance of correlated qubit decay events within a single module and across the physically separated modules. We find that while decay events within one module are strongly correlated (over 85%), events in separate modules only display approximately 2% correlations. We also report coincident decay events in the motherboard and in either of the two daughterboard modules, providing further insight into the nature of these decay events. These results suggest that modular architectures, combined with bespoke errorcorrection codes, offer a promising approach for protecting future quantum processors from chip-scale correlated errors.

Wu, Xuntao [Univ. of Chicago, IL (United States)] ↗
DOE OSTI2024

Smart Pixel Sensors for the HL-LHC

Large-scale particle physics experiments produce tens of terabytes of data every second. Innovative methods to manage the data rate at the HL-LHC, which expects to operate at 10x the luminosity of what the LHC was initially designed for, are needed. AI-on the chip provides a way to intelligently filter out low momentum clusters in the pixel detector. This will open up an opportunity to use the pixel detector for the first time in the CMS Level-1 trigger, and lead to increased sensitivity to new physics measurements and searches. We have taped out our first chip, which incorporates a $p_T$ filtering algorithm on an ASIC chip. Our initial $p_T$ filtering algorithm considers clusters that are tracked by CMS. We will report on ongoing studies seeking to enhance the performance of our filter by utilizing unsupervised learning on untracked clusters, thus increasing background rejection.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade 520__ $$aThe Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

Gong, Datao↗
DOE OSTI2025

Ion Traps and Packaging for Heterogenous Integration - Chimera

Microfabricated surface ion traps and silicon-based photonics are critical technologies for scaling quantum systems. Current ion trap architectures face scalability and integration challenges due to limitations in optical access, fabrication techniques, and material compatibility. State-of-the-art quantum computers and atomic clocks are investigating monolithic integration, which necessitates custom traps for each ion species and has not overcome the integration hurdles presented by merging these technologies. The Chimera (Ion Traps and Packaging for Heterogeneous Integration) project proposes a novel approach utilizing heterogeneous integration (HI) of ion traps and photonic circuits. This separation of components allows for flexibility in ion trap design and reduces fabrication compromises. The Chimera project specifically designed an ion trap to interface vertically with a separately fabricated waveguide chip and demonstrates the first steps to integrating them at the packaging level. The ion trap features a large area of removed silicon, allowing the photonics chip outputs closer to the ion trap, improving alignment and packaging processes. The alignment must be accurate to < 1 µm to ensure that the light from the waveguide can overlap with the trapping region. This fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. By combining separate chips, we demonstrate a new path for scaling trapped ion technology that is less reliant on monolithic integration. We successfully fabricated a trap with a large area of oxide removed, resulting in a region thinned to about 40 µm, a key milestone toward successful integration.

42 ENGINEERING↗
DOE OSTI2025

60 Co γ Irradiation of a CMS CROC v2 to 1.6 Grad

This paper reports the irradiation of the production version of the readout chip for the CMS HL-LHC pixel detector, CROC~v2, to 1.6~Grad using γ s from a 60 Co source at Sandia National Laboratory. The CROC~v2 was kept powered, configured, and maintained as close as possible to its nominal operating temperature of -20~ o C during irradiation. Internal chip voltages, pixel response, and diagnostic ring oscillators were continuously monitored, and thresholds were optimized frequently. The CROC~v2 performed according to specifications at 1.6~Grad. Where available, these results will be compared with those for this and earlier iterations of the RD53 readout chip irradiated to a few Grad with lower-energy X-ray sources.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

A 3D-Printed Millimeter-Wave Inline Waveguide-to-Coplanar-Waveguide Transition to Enable Dense Spectrometer Arrays for Intensity Mapping Surveys

We present a 3D-printed millimeter-wave, octave-bandwidth, in-line waveguide-to-coplanar-waveguide transition designed to enable focal planes with dense arrays of on-chip spectrometers. These arrays will enable compelling surveys of the large-scale structure of the universe through millimeter-wave intensity mapping. The transition consists of a four-step ridge-waveguide transformer that couples light from a rectangular waveguide onto a coplanar waveguide via an electrical connection made with indium bump bonds. We develop a tolerance-aware optimization approach to identify high-performance transition geometries that are robust to manufacturing variations; the same formulation can be applied to other tolerance-sensitive design problems. We also describe the implementation of a custom apparatus and procedure for bump-bonding a silicon chip to a metallized 3D-printed component. We detail the fabrication of the coplanar waveguide chip and three-dimensional waveguide structure, simulations and metrology of a test device, and room temperature reflectance measurements of this device. The room temperature metrology and reflection measurements are consistent with a model that predicts a coupling efficiency of $\mathord{\sim} 95\%$ at cryogenic temperatures in the 85-170 GHz frequency range.

Stover, Austin [Chicago U.; Chicago U., KICP] (ORC↗
DOE OSTI2026

A Graphical User Interface for the Deep Underground Neutrino Experiment Robotic Test Stand

In preparation for DUNE, Fermilab along with six other institutions are testing cold electronics for quality control before components placed in the far detector. We test them by using a robotic arm that places these chips into sockets on a computer board that will test their functionality. Up until now, the chips have been tested using a command line script that drives a state machine to conduct tests step-by-step. In order to lower the skill barrier to conduct tests and to speed up the quality control process, I was tasked to create a graphical user interface that would allow users to use buttons, text boxes, and drop-down menus to input information and tell the testing state machine how to operate. I had to learn about the Python package Tkinter to start the process of widget placement. I further developed a pause feature unused in the previous command line script that would allow the user to shut down testing gracefully, bring the robotic arm to go back to ground state, and go forward or backward a step in the testing process. After completing the basic functionality of the GUI, I started testing production chips with the GUI to debug. Some issues were found, which required me to further develop parts of the inherited state machine code. The code for the GUI has now been pushed into the copy the DUNE/FD_CE git repository and will soon be merged with the official DUNE/FD_CE repository so that the other institutions testing DUNE cold electronics can use and expand upon it.

Gutierrez Villanueva, Jaziel [Fermilab]↗
DOE OSTI2026

Holistic energy analysis method for thermal management architectures of data centers

Modern high-performance computing (HPC) data centers (DCs), particularly those supporting energy-intensive artificial intelligence (AI) workloads, face escalating thermal management challenges that degrade performance through thermal throttling and drive up cooling power consumption and operational costs. To address this challenge, many have developed a wide variety of thermal management solutions (single-phase, two-phase, direct, indirect, hybrid, and more) which attempt to cool HPC DCs effectively while attempting to minimize overall system power consumption. However, the analysis of these solutions and methods to effectively compare one with another is lacking. Overall power usage effectiveness (PUE) and total-power usage effectiveness (TUE) provide a metric to quantify power consumption but fail to identify components in the system which require further optimization. To address this, we propose a holistic analytical framework – the waterfall diagram (WFD) – which leverages a waterfall chart methodology, offering a comprehensive visualization of both the thermal management system loop and heat flow pathways from individual server components to the outdoor ambient. Use of the WFD enables graphical estimations of power efficiency and cooling performance across each component of a DC cooling system and complements Sankey-style energy flow visualizations by additionally resolving stage-wise temperature changes and incremental TUE contributions. The framework is used in conjunction with simulation-based approaches, to conduct a detailed pressure drop and flow distribution analysis aimed at identifying the optimal coolant distribution architecture for a single-phase direct-to-chip water-cooled DC, which serves as the baseline for subsequent WFD analysis. Among the evaluated architectures, the 3 U modular coolant distribution architecture is found to demonstrate the best performance, considering minimal pressure drop and uniform flow distribution. In addition, TUE is calculated for each cooling loop component based on its associated pressure drop and corresponding pumping power, which are integrated into the WFD. This correlation between TUE and local temperature offers immediate insight into the power efficiency and thermal performance contributions of individual components, facilitating further development and optimization. Examples of WFD applications are presented under varying thermal loads and ambient conditions, demonstrating reasonable cooling strategies. Notably, the 3 U modular architecture maintains a consistent chip case temperature of 85°C, achieving a TUE of 1.016 at ambient temperature of 47°C, and a TUE of 1.026 at ambient temperature of 52°C. The WFD methodology provides an efficient, holistic, and streamlined framework for DC thermal management architecture assessment and enables design optimization which is important for addressing the thermal-fluidic energy challenges of current and next-generation DCs.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2026

Synergistic Evolution of Segmental Motion and Cooperative Relaxation within the Amorphous Phase of Organic Mixed Ionic-Electronic Conductors

Organic mixed ionic-electronic conductors (OMIECs) facilitate a variety of electrochemical processes and feature a heterogeneous microstructure composed of both crystalline and amorphous phases. However, structural evolution in amorphous regions during electrochemical doping remains poorly understood, limiting our understanding of mixed conduction mechanisms. Here, in this work, we develop operando chip calorimetry to probe amorphous phase evolution in poly­(3,4-ethylenedioxythiophene):poly­(styrenesulfonate) (PEDOT:PSS) under swelling and electrochemical (de)­doping. Our results reveal that amorphous regions providing ionic transport pathways and those within electronic transport channels undergo heterogeneous, yet synergistic, evolution during electrochemical modulation. The cooperative interplay between segmental motion and relaxation maintains ionic conductivity and intergrain electronic transport upon electrowetting and doping, while facilitating efficient ion hopping and adaptable chain conformations during dedoping. Such synergies are more pronounced in loose structures featuring a fibrillar morphology, which exhibit lower glass transition temperatures (T g ) and higher fragility (m). High-throughput robotic screening further establishes a strong correlation between elevated m/T g ratios and enhanced mixed conduction. These findings elucidate the role of the amorphous phase in the synthesis of OMIECs and underscore the potential of operando chip calorimetry in uncovering structure–property relationships in electroactive polymers.

amorphous phase↗
DOE OSTI2025

A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture

The flourishing development of neural networks that require exponentially growing amounts of data has presented an elevated demand for memory footprint. To address this, researchers have been exploring hardware accelerators with innovative memory architectures like 3D memory. These 3D memory architectures offer enhanced storage capacity and processing capabilities, at a cost of rising on-chip temperature during operation. Hafnium Zirconium Oxide (HZO) based Ferroelectric Random Access Memory (FeRAM) is a promising nonvolatile memory candidate in neural network hardware accelerators for its outstanding write performance and reliability. However, its implementation in the architecture regarding the temperature-dependent ferroelectric switching behavior has not been well studied. In this work, we study the thermal impacts on polarization switching through experimental devices and simulation results. We conduct the circuit and architecture-level simulations to showcase that one can exploit this temperature rise to reduce FeRAM's write voltage and write energy due to its unique temperature-activated polarization switching mechanisms. As the on-chip temperature increases to 351K (ambient temperature at 300K) due to neural network workloads, the access energy per bit can be reduced by 27.6% when a dynamic write voltage is applied.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Scalable Nanoimprint Manufacturing of Functional Multilayer Metasurface Devices

Optical metasurfaces, consisting of subwavelength-scale meta-atom arrays, hold great promise of overcoming the fundamental limitations of conventional optics. Due to their structural complexity, metasurfaces usually require high-resolution yet slow and expensive fabrication processes. Here, using a metasurface polarimetric imaging device as an example, the photonic structures and the Nanoimprint lithography (NIL) processes are designed, creating two separate NIL molds over a patterning area of > 20 mm2 with designed Moiré alignment markers by electron-beam writing, and further subsequently integrate silicon and aluminum metasurface structures on a chip. Uniquely, the silicon and aluminum metasurfaces are fabricated by using the nanolithography and 3D pattern-transfer capabilities of NIL, respectively, achieving nanometer-scale linewidth uniformity, sub-200 nm translational overlay accuracy, and <0.017 rotational alignment error while significantly reducing fabrication complexity and surface roughness. Here, the micro-sized multilayer metasurfaces have high circular polarization extinction ratios as large as ≈20 and ≈80 in blue and red wavelengths. Further, the metasurface chip-integrated CMOS imager demonstrates high accuracy in broad-band, full Stokes parameter analysis in the visible wavelength ranges and single-shot polarimetric imaging. This novel, NIL-based, multilayered nanomanufacturing approach is applicable to the scalable production of large-area functional structures for ultra-compact optic, electronic, and quantum devices.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Frequency‐Locked Wireless Multifunctional Surface Acoustic Wave Sensors

Abstract Surface acoustic waves (SAWs) have shown great potential for developing sensors for structural health monitoring (SHM) and lab‐on‐a‐chip (LOC) applications. Existing SAW sensors mainly rely on measuring the frequency shifts of high‐frequency (e.g., >0.1 GHz) resonance peaks. This study presents frequency‐locked wireless multifunctional SAW sensors that enable multiple wireless sensing functions, including strain sensing, temperature measurement, water presence detection, and vibration sensing. These sensors leverage SAW resonators on piezoelectric chips, inductive coupling‐based wireless power transmission, and, particularly, a frequency‐locked wireless sensing mechanism that works at low frequencies (e.g., <0.1 GHz). This mechanism locks the input frequency on the slope of a sensor's reflection spectrum and monitors the reflection signal's amplitude change induced by the changes of sensing parameters. The proof‐of‐concept experiments show that these wireless sensors can operate in a low‐power active mode for on‐demand wireless strain measurement, temperature sensing, and water presence detection. Moreover, these sensors can operate in a power‐free passive mode for vibration sensing, with results that agree well with laser vibrometer measurements. It is anticipated that the designs and mechanisms of the frequency‐locked wireless SAW sensors will inspire researchers to develop future wireless multifunctional sensors for SHM and LOC applications.

Bo, Luyu↗
DOE OSTI2024

Evolution of Dissipative Regimes in Atomically Thin Bi 2 Sr 2 CaCu 2 O 8 + x Superconductor

Thermoelectric transport is widely used to study Abrikosov vortex dynamics in unconventional superconductors. However, only a few thermoelectric studies have been conducted near the dimensional crossover that occurs when the vortex-vortex interaction length scale becomes comparable to the sample size. Here, the effects of finite size on the dissipation mechanisms of the Nernst effect in the optimally doped Bi 2 Sr 2 CaCu 2 O 8 + x high-temperature superconductor are reported, down to the atomic length limit. To access this regime, a new generation of thermoelectric chips based on silicon nitride microprinted circuit boards is developed. These chips ensure optimized signals while preventing sample deterioration. The results demonstrate that lateral confinement at the nanoscale can effectively reduce vortex dissipation. Investigating vortex dissipation at the micro- and nano-scale is essential for creating stable, miniaturized superconducting circuits.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗