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At least 109 records · Page 6

Impacts of Hybrid Parallelism and Vectorization on the Performance of Newton-Krylov Methods in Computational Aerodynamics

Finding the numerical solution of moderate and high-fidelity aerodynamics problems on modern computer architectures involves, 1) decomposing the domain into smaller regions of nearly equal size, and 2) allocating computational resources for calculations on each domain and communication between domains. Modern computer clusters are composed from hierarchies of processing, memory, and communication resources with varying capabilities and latencies.This paper focuses on the combination of domain decomposition provided by ParMETIS [1]and Newton-Krylov Methods [2–5] for the solution of Computational Aerodynamics problems of interest to NASA. Herein, trade-offs encountered when mapping aerodynamics problems to modern computer architectures are explored through examples and discussions of trade-offs in parallelism from MPI [6], Open MP [7], and vectorization as partition sizes and computational resources are varied. An example of the impact that domain decomposition and MPI+OpenMPresource allocation can have on an adjoint calculation is presented in this abstract. The full paper will include more detailed examples, discussions of difficulties and potential methods to overcome them, and topics identified for future study.

Computational Aerodynamics, Hybrid Parallelism, Ve↗

Assessment of Edge-Based Viscous Method for Corner-Flow Solutions on Graphics Processing Units

A highly efficient, edge-based viscous (EBV) discretization method has been recently implemented in a practical, unstructured-grid, node-centered, finite-volume flow solver and evaluated for Reynolds-averaged Navier-Stokes (RANS) formulations. In comparison to a well-established cell-based viscous (CBV) method, the EBV method has demonstrated multifold acceleration of all viscous-kernel computations on general unstructured mixed-element grids. The viscous kernels include evaluation of viscous fluxes, diffusion terms in turbulence models, and the corresponding Jacobian terms. In this paper, an EBV implementation of a nonlinear extension of the Spalart-Allmaras turbulence model, SA-neg-QCR2000, is presented and verified. The SA-neg-QCR2000 model is used for simulating turbulent corner flows. Previously reported EBV computations have been conducted on traditional computing architectures based on central processing units (CPU). This paper assesses benefits of the EBV method on modern high-performance computing architectures based on graphics processing units (GPU). The GPU implementations of the CBV and EBV methods are verified by comparing solutions and iterative convergence with those observed in CPU computations on the same grids. A comprehensive assessment of the EBV speedup on CPU and GPU architectures is presented for established benchmark corner flows, namely, a supersonic flow through a long square duct and a subsonic flow around a NASA juncture flow model.

CFD↗

Assessment of Edge-Based Viscous Method for Corner-Flow Solutions on Graphics Processing Units

A highly efficient, edge-based viscous (EBV) discretization method has been recently implemented in a practical, unstructured-grid, node-centered, finite-volume flow solver and evaluated for Reynolds-averaged Navier-Stokes (RANS) formulations. In comparison to a well-established cell-based viscous (CBV) method, the EBV method has demonstrated multifold acceleration of all viscous-kernel computations on general unstructured mixed-element grids. The viscous kernels include evaluation of viscous fluxes, diffusion terms in turbulence models, and the corresponding Jacobian terms. In this paper, an EBV implementation of a nonlinear extension of the Spalart-Allmaras turbulence model, SA-neg-QCR2000, is presented and verified. The SA-neg-QCR2000 model is used for simulating turbulent corner flows. Previously reported EBV computations have been conducted on traditional computing architectures based on central processing units (CPU). This paper assesses benefits of the EBV method on modern high-performance computing architectures based on graphics processing units (GPU). The GPU implementations of the CBV and EBV methods are verified by comparing solutions and iterative convergence with those observed in CPU computations on the same grids. A comprehensive assessment of the EBV speedup on CPU and GPU architectures is presented for established benchmark corner flows, namely, a supersonic flow through a long square duct and a subsonic flow around a NASA juncture flow model.

CFD↗

VLSI architectures for computing multiplications and inverses in GF(2m)

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Wang, C. C.↗

VLSI architectures for computing multiplications and inverses in GF(2-m)

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Wang, C. C.↗

HiMAT onboard flight computer system architecture and qualification

Two highly maneuverable aircraft technology (HiMAT) remotely piloted research vehicles (RPRV's) are being flight tested at NASA Dryden Flight Research Center, Edwards, California, to demonstrate and evaluate a number of technological advances applicable to future fighter aircraft. Closed-loop primary flight control is performed from a ground-based cockpit utilizing a digital computer and up/down telemetry links. A backup flight control system for emergency operation resides in one of two onboard computers. Other functions of the onboard computer system are uplink processing, downlink processing, engine control, failure detection, and redundancy management. This paper describes the architecture, functions, and flight qualification of the HiMAT onboard flight computer systems.

Myers, A. F.↗

The NIST Real-Time Control System (RCS): A Reference Model Architecture for Computational Intelligence

The Real-time Control System (RCS) developed at NIST and elsewhere over the past two decades defines a reference model architecture for design and analysis of complex intelligent control systems. The RCS architecture consists of a hierarchically layered set of functional processing modules connected by a network of communication pathways. The primary distinguishing feature of the layers is the bandwidth of the control loops. The characteristic bandwidth of each level is determined by the spatial and temporal integration window of filters, the temporal frequency of signals and events, the spatial frequency of patterns, and the planning horizon and granularity of the planners that operate at each level. At each level, tasks are decomposed into sequential subtasks, to be performed by cooperating sets of subordinate agents. At each level, signals from sensors are filtered and correlated with spatial and temporal features that are relevant to the control function being implemented at that level.

Albus, James S.↗

A Multi-Level Parallelization Concept for High-Fidelity Multi-Block Solvers

The integration of high-fidelity Computational Fluid Dynamics (CFD) analysis tools with the industrial design process benefits greatly from the robust implementations that are transportable across a wide range of computer architectures. In the present work, a hybrid domain-decomposition and parallelization concept was developed and implemented into the widely-used NASA multi-block Computational Fluid Dynamics (CFD) packages implemented in ENSAERO and OVERFLOW. The new parallel solver concept, PENS (Parallel Euler Navier-Stokes Solver), employs both fine and coarse granularity in data partitioning as well as data coalescing to obtain the desired load-balance characteristics on the available computer platforms. This multi-level parallelism implementation itself introduces no changes to the numerical results, hence the original fidelity of the packages are identically preserved. The present implementation uses the Message Passing Interface (MPI) library for interprocessor message passing and memory accessing. By choosing an appropriate combination of the available partitioning and coalescing capabilities only during the execution stage, the PENS solver becomes adaptable to different computer architectures from shared-memory to distributed-memory platforms with varying degrees of parallelism. The PENS implementation on the IBM SP2 distributed memory environment at the NASA Ames Research Center obtains 85 percent scalable parallel performance using fine-grain partitioning of single-block CFD domains using up to 128 wide computational nodes. Multi-block CFD simulations of complete aircraft simulations achieve 75 percent perfect load-balanced executions using data coalescing and the two levels of parallelism. SGI PowerChallenge, SGI Origin 2000, and a cluster of workstations are the other platforms where the robustness of the implementation is tested. The performance behavior on the other computer platforms with a variety of realistic problems will be included as this on-going study progresses.

Hatay, Ferhat F.↗

Parallel algorithms and architecture for computation of manipulator forward dynamics

Parallel computation of manipulator forward dynamics is investigated. Considering three classes of algorithms for the solution of the problem, that is, the O(n), the O(n exp 2), and the O(n exp 3) algorithms, parallelism in the problem is analyzed. It is shown that the problem belongs to the class of NC and that the time and processors bounds are of O(log2/2n) and O(n exp 4), respectively. However, the fastest stable parallel algorithms achieve the computation time of O(n) and can be derived by parallelization of the O(n exp 3) serial algorithms. Parallel computation of the O(n exp 3) algorithms requires the development of parallel algorithms for a set of fundamentally different problems, that is, the Newton-Euler formulation, the computation of the inertia matrix, decomposition of the symmetric, positive definite matrix, and the solution of triangular systems. Parallel algorithms for this set of problems are developed which can be efficiently implemented on a unique architecture, a triangular array of n(n+2)/2 processors with a simple nearest-neighbor interconnection. This architecture is particularly suitable for VLSI and WSI implementations. The developed parallel algorithm, compared to the best serial O(n) algorithm, achieves an asymptotic speedup of more than two orders-of-magnitude in the computation the forward dynamics.

Fijany, Amir↗

Digital optical computers at the optoelectronic computing systems center

The Digital Optical Computing Program within the National Science Foundation Engineering Research Center for Opto-electronic Computing Systems has as its specific goal research on optical computing architectures suitable for use at the highest possible speeds. The program can be targeted toward exploiting the time domain because other programs in the Center are pursuing research on parallel optical systems, exploiting optical interconnection and optical devices and materials. Using a general purpose computing architecture as the focus, we are developing design techniques, tools and architecture for operation at the speed of light limit. Experimental work is being done with the somewhat low speed components currently available but with architectures which will scale up in speed as faster devices are developed. The design algorithms and tools developed for a general purpose, stored program computer are being applied to other systems such as optimally controlled optical communication networks.

Jordan, Harry F.↗

High End Computing Technologies for Earth Science Applications: Trends, Challenges, and Innovations

Earth science applications of the future will stress the capabilities of even the highest performance supercomputers in the areas of raw compute power, mass storage management, and software environments. These NASA mission critical problems demand usable multi-petaflops and exabyte-scale systems to fully realize their science goals. With an exciting vision of the technologies needed, NASA has established a comprehensive program of advanced research in computer architecture, software tools, and device technology to ensure that, in partnership with US industry, it can meet these demanding requirements with reliable, cost effective, and usable ultra-scale systems. NASA will exploit, explore, and influence emerging high end computing architectures and technologies to accelerate the next generation of engineering, operations, and discovery processes for NASA Enterprises. This article captures this vision and describes the concepts, accomplishments, and the potential payoff of the key thrusts that will help meet the computational challenges in Earth science applications.

Parks, John↗

A laboratory breadboard system for dual-arm teleoperation

The computing architecture of a novel dual-arm teleoperation system is described. The novelty of this system is that: (1) the master arm is not a replica of the slave arm; it is unspecific to any manipulator and can be used for the control of various robot arms with software modifications; and (2) the force feedback to the general purpose master arm is derived from force-torque sensor data originating from the slave hand. The computing architecture of this breadboard system is a fully synchronized pipeline with unique methods for data handling, communication and mathematical transformations. The computing system is modular, thus inherently extendable. The local control loops at both sites operate at 100 Hz rate, and the end-to-end bilateral (force-reflecting) control loop operates at 200 Hz rate, each loop without interpolation. This provides high-fidelity control. This end-to-end system elevates teleoperation to a new level of capabilities via the use of sensors, microprocessors, novel electronics, and real-time graphics displays. A description is given of a graphic simulation system connected to the dual-arm teleoperation breadboard system. High-fidelity graphic simulation of a telerobot (called Phantom Robot) is used for preview and predictive displays for planning and for real-time control under several seconds communication time delay conditions. High fidelity graphic simulation is obtained by using appropriate calibration techniques.

Bejczy, A. K.↗

The science of computing - Parallel computation

Although parallel computation architectures have been known for computers since the 1920s, it was only in the 1970s that microelectronic components technologies advanced to the point where it became feasible to incorporate multiple processors in one machine. Concommitantly, the development of algorithms for parallel processing also lagged due to hardware limitations. The speed of computing with solid-state chips is limited by gate switching delays. The physical limit implies that a 1 Gflop operational speed is the maximum for sequential processors. A computer recently introduced features a 'hypercube' architecture with 128 processors connected in networks at 5, 6 or 7 points per grid, depending on the design choice. Its computing speed rivals that of supercomputers, but at a fraction of the cost. The added speed with less hardware is due to parallel processing, which utilizes algorithms representing different parts of an equation that can be broken into simpler statements and processed simultaneously. Present, highly developed computer languages like FORTRAN, PASCAL, COBOL, etc., rely on sequential instructions. Thus, increased emphasis will now be directed at parallel processing algorithms to exploit the new architectures.

Denning, P. J.↗

NASTRAN of the HEP

Preliminary plans for the conversion of NASTRAN to DENELCOR's heterogeneous element processor (HEP) are presented. First, a brief history of computer architecture and the architecture of the HEP computer system are discussed. Second, a description of the HEP computer system is provided. Lastly, the preliminary NASTRAN conversion plans for link management, I/O management, memory management, and code optimization are discussed.

Brown, W. K.↗

Algorithms for Finite-Element Equations

Five direct and five iterative algorithms for finite element equations in linear equilibrium problems investigated for number of parallel computer architectures and their basic computation methods compared.

Salama, M. A.↗

Reliability models for dataflow computer systems

The demands for concurrent operation within a computer system and the representation of parallelism in programming languages have yielded a new form of program representation known as data flow (DENN 74, DENN 75, TREL 82a). A new model based on data flow principles for parallel computations and parallel computer systems is presented. Necessary conditions for liveness and deadlock freeness in data flow graphs are derived. The data flow graph is used as a model to represent asynchronous concurrent computer architectures including data flow computers.

Kavi, K. M.↗

Inter-computer communication architecture for a mixed redundancy distributed system

The triply redundant intercomputer network for the Advanced Information Processing System (AIPS), an architecture developed to serve as the core avionics system for a broad range of aerospace vehicles, is discussed. The AIPS intercomputer network provides a high-speed, Byzantine-fault-resilient communication service between processing sites, even in the presence of arbitrary failures of simplex and duplex processing sites on the IC network. The IC network contention poll has evolved from the Laning Poll. An analysis of the failure modes and effects and a simulation of the AIPS contention poll, demonstrate the robustness of the system.

Lala, Jaynarayan H.↗