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At least 109 records · Page 6

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NASA NTRS2011

Radiation-Tolerant, SpaceWire-Compatible Switching Fabric

Current and future near-Earth and deep space exploration programs and space defense programs require the development of robust intra-spacecraft serial data transfer electronics that must be reconfigurable, fault-tolerant, and have the ability to operate effectively for long periods of time in harsh environmental conditions. Existing data transfer systems based on state-of-the-art serial data transfer protocols or passive backplanes are slow, power-hungry, and poorly reconfigurable. They provide limited expandability and poor tolerance to radiation effects and total ionizing dose (TID) in particular, which presents harmful threats to modern submicron electronics. This novel approach is based on a standard library of differential cells tolerant to TID, and patented, multi-level serial interface architecture that ensures the reliable operation of serial interconnects without application of a data-strobe or other encoding techniques. This proprietary, high-speed differential interface presents a lowpower solution fully compatible with the SpaceWire (SW) protocol. It replaces a dual data-strobe link with two identical independent data channels, thus improving the system s tolerance to harsh environments through additional double redundancy. Each channel incorporates an automatic line integrity control circuitry that delivers error signals in case of broken or shorted lines.

Katzman, Vladimir↗

NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗

NASA NTRS2006

Arcing in Leo and Geo Simulated Environments: Comparative Analysis

Comprehensive tests of two solar array samples in simulated Low Earth Orbit (LEO) and Geosynchronous Orbit (GEO) environments have demonstrated that the arc inception voltage was 2-3 times lower in the LEO plasma than in the GEO vacuum. Arc current pulse wave forms are also essentially different in these environments. Moreover, the wide variations of pulse forms do not allow introducing the definition of a "standard arc wave form" even in GEO conditions. Visual inspection of the samples after testing in a GEO environment revealed considerable damage on coverglass surfaces and interconnects. These harmful consequences can be explained by the discharge energy being one order of magnitude higher in vacuum than in background plasma. The tests also revealed a potential danger of powerful electrostatic discharges that could be initiated on the solar array surface of a satellite in GEO during the ignition of an arcjet thruster.

Vayner, Boris V.↗

NASA NTRS2005

Video Mosaicking for Inspection of Gas Pipelines

A vision system that includes a specially designed video camera and an image-data-processing computer is under development as a prototype of robotic systems for visual inspection of the interior surfaces of pipes and especially of gas pipelines. The system is capable of providing both forward views and mosaicked radial views that can be displayed in real time or after inspection. To avoid the complexities associated with moving parts and to provide simultaneous forward and radial views, the video camera is equipped with a wide-angle (>165 ) fish-eye lens aimed along the axis of a pipe to be inspected. Nine white-light-emitting diodes (LEDs) placed just outside the field of view of the lens (see Figure 1) provide ample diffuse illumination for a high-contrast image of the interior pipe wall. The video camera contains a 2/3-in. (1.7-cm) charge-coupled-device (CCD) photodetector array and functions according to the National Television Standards Committee (NTSC) standard. The video output of the camera is sent to an off-the-shelf video capture board (frame grabber) by use of a peripheral component interconnect (PCI) interface in the computer, which is of the 400-MHz, Pentium II (or equivalent) class. Prior video-mosaicking techniques are applicable to narrow-field-of-view (low-distortion) images of evenly illuminated, relatively flat surfaces viewed along approximately perpendicular lines by cameras that do not rotate and that move approximately parallel to the viewed surfaces. One such technique for real-time creation of mosaic images of the ocean floor involves the use of visual correspondences based on area correlation, during both the acquisition of separate images of adjacent areas and the consolidation (equivalently, integration) of the separate images into a mosaic image, in order to insure that there are no gaps in the mosaic image. The data-processing technique used for mosaicking in the present system also involves area correlation, but with several notable differences: Because the wide-angle lens introduces considerable distortion, the image data must be processed to effectively unwarp the images (see Figure 2). The computer executes special software that includes an unwarping algorithm that takes explicit account of the cylindrical pipe geometry. To reduce the processing time needed for unwarping, parameters of the geometric mapping between the circular view of a fisheye lens and pipe wall are determined in advance from calibration images and compiled into an electronic lookup table. The software incorporates the assumption that the optical axis of the camera is parallel (rather than perpendicular) to the direction of motion of the camera. The software also compensates for the decrease in illumination with distance from the ring of LEDs.

Magruder, Darby↗

NASA NTRS1972

Development of a flat cable system

A flat conductor cabling system for electrical/electronic interwiring is described. Six major items comprise the system: the cables, splices - one for flat cable to round wires and one for flat cable to flat cable; a series of flat cable connectors; the distributor, which is used for interconnecting the circuits; and a repair technique for the falt cable. Polyarylene, a new high performance melt-processable insulation material, permits the design of a completely standardized, modular flat conductor flat cable. The development of an advanced heat-shrinkable plastics technology involving the use of selectively bonded plastic film has resulted in the multiple termination module, used for making high-reliability sealed solder terminations to either flat conductor cable or round wires. All necessary tools and application equipment are included in the system design.

Neel, R. M.↗

NASA NTRS1992

An OSI architecture for the Deep Space Network

This article presents an Open Systems Interconnection (OSI) architecture developed for the Deep Space Network. An historical review is provided to establish the context for current United States Government policy on interprocessor communication standards. An introduction to the OSI architecture, its seven-layer approach, and an overview of application service entities are furnished as a tutorial. Finally, the results of a prototype system developed for monitor and control of a Deep Space Station are also presented.

Heuser, W. R.↗

NASA NTRS1997

Crew Member Interface with Space Station Furnace Facility

The Space Station Furnace Facility (SSFF) is a facility located in the International Space Station United States Laboratory (ISS US Lab) for materials research in the microgravity environment. The SSFF will accommodate basic research, commercial applications, and studies of phenomena of metals and alloys, electronic and photonic materials, and glasses and ceramics. To support this broad base of research requirements, the SSFF will operate, regulate, and support a variety of Experiment Modules (EMs). To meet station requirements concerning the microgravity level needed for experiments, station is providing an active vibration isolation system, and SSFF provides the interface. SSFF physically consists of a Core Rack and two instrument racks (IRs) that occupy three adjacent ISS US Lab rack locations within the International Space Station (ISS). All SSFF racks are modified International Standard Payload Racks (ISPR). SSFF racks will have a 50% larger pass through area on the lower sides than ISPRs to accommodate the many rack to rack interconnections. The Instrument Racks are further modified with lowered floors and an additional removable panel (15" x 22") on top of the rack for access if needed. The Core Rack shall contain all centralized Core subsystems and ISS subsystem equipment. The two Instrument Racks shall contain the distributed Core subsystem equipment, ISS subsystem equipment, and the EMs. The Core System, which includes the Core Rack, the IR structures, and subsystem components located in the IRs serves as the central control and management for the IRs and the EMs. The Core System receives the resources provided by the International Space Station (ISS) and modifies, allocates, and distributes these resources to meet the operational requirements of the furnace. The Core System is able to support a total of four EMs and can control, support, and activate/deactivate the operations of two EMs, simultaneously. The IRs can be configured to house two small EMs or one tall vertical EM, and serve as the interface between the Core and the respective EM. The Core Rack and an adjacent Instrument Rack (containing one or more furnaces) will be delivered to the ISS in one launch. This is Integrated Configuration One (ICI). The Core Rack and IRI will be passive during transport in the Mini Pressurized Logistics Module (MPLM): Any subsequent EMs to operate within IRI are installed on-orbit. The second IR (containing one or more furnaces) is delivered to ISS on a subsequent launch which will establish Integrated Configuration Two (IC2). Additional integrated configurations will be established with the replacement of EMs or Instrument Racks.

Cash, Martha B.↗

NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗

NASA NTRS2009

Efficient Multiplexer FPGA Block Structures Based on G4FETs

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Vatan, Farrokh↗

NASA NTRS1977

Standard high-reliability integrated circuit logic packaging

A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

Slaughter, D. W.↗

NASA NTRS1988

Future MAUS payload and the TWIN-MAUS configuration

The German MAUS project (materials science autonomous experiments in weightlessness) was initiated in 1979 for optimum utilization of NASA's Get Away Special (GAS) program. The standard MAUS system was developed to meet GAS requirements and can accommodate a wide variety of GAS-type experiments. The system offers a range of services to experimenters within the framework of standardized interfaces. Four MAUS payloads being prepared for future space shuttle flight opportunities are described. The experiments include critical Marangoni convection, oscillatory Marangoni convection, pool boiling, and gas bubbles in glass melts. Scientific objectives as well as equipment hardware are presented together with recent improvements to the MAUS standard system, e.g., a new experiment control and data management unit and a semiconductor memory. A promising means of increasing resources in the field of GAS experiments is the interconnection of GAS containers. This important feature has been studied to meet the challenge of future advanced payloads. In the TWIN-MAUS configuration, electrical power and data will be transferred between two containers mounted adjacent to each other.

Staniek, S.↗

NASA NTRS1975

Real-time computer data system for the 40- by 80-foot wind tunnel facility at Ames Research Center

The background material and operational concepts of a computer-based system for an operating wind tunnel are described. An on-line real-time computer system was installed in a wind tunnel facility to gather static and dynamic data. The computer system monitored aerodynamic forces and moments of periodic and quasi-periodic functions, and displayed and plotted computed results in real time. The total system is comprised of several off-the-shelf, interconnected subsystems that are linked to a large data processing center. The system includes a central processor unit with 32,000 24-bit words of core memory, a number of standard peripherals, and several special processors; namely, a dynamic analysis subsystem, a 256-channel PCM-data subsystem and ground station, a 60-channel high-speed data acquisition subsystem, a communication link, and static force and pressure subsystems. The role of the test engineer as a vital link in the system is also described.

Cambra, J. M.↗

NASA NTRS1990

Qualification and life testing of a flight design hydrazine arcjet system

This paper describes the design and the requirements of a low-power hydrazine arc jet system and presents the results of tests on the system's performance, vibration, and lifetime. The system consists of an arcjet, catalyst bed, power control unit, and interconnecting power cable. Operating at 1.4 kW input power, the system provides a minimum of 450 sec mission average specific impulse, yielding greater than a 100 kg propellant savings over standard monopropellant or bipropellant systems used on communication satellites.

Knowles, S. C.↗

NASA NTRS1985

Selective broadcast interconnection - A novel scheme for fiber-optic local-area networks

A passive, unswitched scheme is introduced for directly interconnecting N stations, each of which has C transmitters and receivers. Implementations using fiber optics with spatial multiplexing and optionally wavelength multiplexing are discussed. This scheme utilizes the same resources as standard topologies with C parallel buses but outperforms them in two respects: (1) the aggregate throughput is proportional to C squared rather than to C; and (2) the power of each transmitter need reach only N/C, instead of N, receivers.

Marhic, M. E.↗

NASA NTRS2009

Smart and Intelligent Sensors

John C. Stennis Space Center (SSC) provides rocket engine propulsion testing for NASA's space programs. Since the development of the Space Shuttle, every Space Shuttle Main Engine (SSME) has undergone acceptance testing at SSC before going to Kennedy Space Center (KSC) for integration into the Space Shuttle. The SSME is a large cryogenic rocket engine that uses Liquid Hydrogen (LH2) as the fuel. As NASA moves to the new ARES V launch system, the main engines on the new vehicle, as well as the upper stage engine, are currently base lined to be cryogenic rocket engines that will also use LH2. The main rocket engines for the ARES V will be larger than the SSME, while the upper stage engine will be approximately half that size. As a result, significant quantities of hydrogen will be required during the development, testing, and operation of these rocket engines.Better approaches are needed to simplify sensor integration and help reduce life-cycle costs. 1.Smarter sensors. Sensor integration should be a matter of "plug-and-play" making sensors easier to add to a system. Sensors that implement new standards can help address this problem; for example, IEEE STD 1451.4 defines transducer electronic data sheet (TEDS) templates for commonly used sensors such as bridge elements and thermocouples. When a 1451.4 compliant smart sensor is connected to a system that can read the TEDS memory, all information needed to configure the data acquisition system can be uploaded. This reduces the amount of labor required and helps minimize configuration errors. 2.Intelligent sensors. Data received from a sensor be scaled, linearized; and converted to engineering units. Methods to reduce sensor processing overhead at the application node are needed. Smart sensors using low-cost microprocessors with integral data acquisition and communication support offer the means to add these capabilities. Once a processor is embedded, other features can be added; for example, intelligent sensors can make a health assessment to inform the data acquisition client when sensor performance is suspect. 3.Distributed sample synchronization. Networks of sensors require new ways for synchronizing samples. Standards that address the distributed timing problem (for example, IEEE STD 1588) provide the means to aggregate samples from many distributed smart sensors with sub-microsecond accuracy. 4. Reduction in interconnect. Alternative means are needed to reduce the frequent problems associated with cabling and connectors. Wireless technologies offer the promise of reducing interconnects and simultaneously making it easy to quickly add a sensor to a system.

Lansaw, John↗

NASA NTRS1980

Simulator results of an F-14A airplane utilizing an aileron-rudder interconnect during carrier approaches and landings

A piloted simulator study was conducted to evaluate an aileron rudder interconnect (ARI) control system for the F-14A airplane in the landing configuration. Effects on pilot performance and handling characteristics were investigated. Two ARI configurations were tested and compared to the standard F-14 fleet control system. A nonlinear aerodynamic model of the F-14 was used in conjunction with a six degree of freedom motion base simulator. The evaluation task, which utilized three subject pilots, consistent of a night carrier approach and landing. Both ARI configurations produced improved pilot performance and pilot ratings when compared to the standard control system. Sideslip due to adverse yaw as considerably reduced by the ARI systems and heading control was more stable and precise. Lateral deviation from centerline was reduced during the approach and lateral touchdown dispersion on the carrier deck was reduced with the ARI control systems.

Kelly, W. W.↗

NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) developed and previously characterized a photon-counting optical ground receiver system. The receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization High Photon Efficiency (HPE) Standard. The standard will be used on the Optical Artemis-2 Orion (O2O) communications demonstration and the Deep Space Optical Communication (DSOC) project aboard the Psyche spacecraft. The receiver system consists of a fiber interconnect, up to sixteen superconducting nanowire single-photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Previously, the receiver system architecture was described and test results without emulated link effects were presented. SNSPD device properties, which impact detection jitter and time delay, can limit the receiver dynamic range, especially when operating with varying flux rates (>10 dB) between detectors. Codeword error-rate curves with and without simulated clock drifts attributed to Doppler shift and space transmitter clock differences are presented. Results with ±66 ppm clock differences show minimal performance impact (<0.2 dB). Test results show that the receiver dynamic range (>28 dB) is limited by changing SNSPD detection delays at high photon flux rates.

optical communications↗

NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

optical communications↗