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NASA NTRS1983

Brief characterization of germanium junction field effect transistors (FETs) at 77, 4, and 1.8 K

In the case of modern infrared focal planes, one of the major problems is related to the noise contribution of the cooled, impedance-matching device used as the preamplifier stage in the detector electronics system. An ideal preamp device should have the low-noise advantages of a buried-channel device and operate isothermally with the low-temperature detector array. The Ge JFET might provide this ideal device. A testing program with Ge JFETs is discussed. It is concluded that germanium JFETs offer an attractive alternative for cryogenic preamplifier designs. They operate well with high transconductance and low noise at LHe temperatures. It is believed that these devices point the way for the development of large, integrated-array, long wavelength, infrared focal planes which incorporate germanium detectors, germanium load resistors, and germanium preamplifiers within the same monolithic structure.

Arentz, R. F.↗

NASA NTRS2004

A Two-Dimensional, Semiconducting Bolometer Array for HAWC

The Stratospheric Observatory For Infrared Astronomy's (SOFIA's) High resolution Airborne Wideband Camera (HAWC) will use an ion-implanted silicon bolometer array developed at NASA s Goddard Space Flight Center (GSFC). The GSFC Pop-Up Detectors (PUDs) use a unique folding technique to enable a 12 x 32 element closepacked array of bolometers with a filling factor greater than 95%. The HAWC detector uses a resistive metal film on silicon to provide frequency independent, approx. 50% absorption over the 40 - 300 micron band. The silicon bolometers are manufactured in 32-element rows within silicon frames using Micro Electro Mechanical Systems (MEMS) silicon etching techniques. The frames are then cut, "folded", and glued onto a metallized, ceramic, thermal bus "bar". Optical alignment using micrometer jigs ensures their uniformity and correct placement. The rows are then stacked side-by-side to create the final 12 x 32 element array. A kinematic Kevlar suspension system isolates the 200 mK bolometer cold stage from the rest of the 4K detector housing. GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The Junction Field Effect Transistor (JFET) preamplifiers for all the signal channels operate at 120 K, yet they are electrically connected and located in close proximity to the bolometers. The JFET module design provides sufficient thermal isolation and heat sinking for these, so that their heat is not detected by the bolometers. Preliminary engineering results from the flight detector dark test run are expected to be available in July 2004. This paper describes the array assembly and mechanical and thermal design of the HAWC detector and the JFET module.

Voellmer, George M.↗

NASA NTRS2009

SiC Optically Modulated Field-Effect Transistor

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.

Tabib-Azar, Massood↗

NASA NTRS2010

IXO-XMS LVSID Anti-Coincidence Detector

This document describes a high-TRL backup implementation of the anti-coincidence detector for the IXO/XMS instrument. The backup detector, hereafter referred to as the low-voltage silicon ionization detector (LVSID), has been successfully flown on Astro-E2 (Suzaku)/XRS and is currently being implemented, without significant changes, on the Astro-H/SXS instrument. The LVSID anti-coincidence detector on Astro-E2/XRS operated successfully for almost 2 years, and was not affected by the loss of liquid helium in that instrument. The LVSID continues to operate after almost 5 years on-orbit (LEO, 550 km) but with slightly increased noise following the expected depletion of solid Neon after 22 months. The noise of the device is increased after the loss of sNe due to thermally induced bias and readout noise. No radiation damage, or off-nominal affects have been observed with the LVSID on-orbit during the Astro-E2/XRS program. A detector die from the same fabrication run will be used on the Astro-H/SXS mission. The LVSID technology and cryogenic JFET readout system is thus TRL 9. The technology is described in detail in section 2. The IXO/XMS "backup-up" anti-coincidence detector is a small array of LVSID detectors that are almost identical to those employed for Astro -E2/XRS as described in this document. The readout system is identical and, infact would use the same design as the Astro -E2/XRS JFET amplifier module (19 channels) essentially without changes except for its mechanical mount. The changes required for the IXO/XMS LVSID array are limited to the mounting of the LVSID detectors, and the mechanical mounting of the JFET amplifier sub-assembly. There is no technical development needed for the IXO/XMS implementation and the technology is ready for detailed design-work leading to PDR. The TRL level is thus at least 6, and possibly higher. Characteristics of an IXO/XMS LVSID anti-co detector are given in Table 1 and described in detail in section 3.

Porter, Scott F.↗

DOE OSTI2020

High voltage MOSFET devices and methods of making the devices

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

42 ENGINEERING↗

NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗

DOE OSTI2023

Selective area doping of GaN toward high-power applications

Abstract Selective area doping in GaN, especially p-type, is a critical and inevitable building block for the realization of advanced device structures for high-power applications, including, but not limited to, current-aperture vertical electron transistors, junction termination extensions, junction barrier Schottky diodes, junction field-effect transistors (JFETs), vertical-channel JFETs, U-shaped metal–oxide–semiconductor field-effect transistors (U-MOSFETs), and Fin MOSFETs. This paper reviews and summarizes some of the recent advances in the fields of selective area etching and regrowth, ion implantation, and polarity-dependent doping that may lead to the practical realization of GaN-based power devices.

Physics↗

DOE OSTI2021

Radiation-Hardened Instrumentation, Sensors and Electronics

To assist the US Department of Energy in defining a course for Office of Nuclear Energy–funded radiation-hardened (rad-hard) electronics research, Oak Ridge National Laboratory (ORNL) will focus on three main tasks in FY21. The first task will investigate the survivability of silicon junction-gate field-effect transistors (Si-JFETs) through a 100 Mrad total ionizing dose (TID) experiment and report the test results. The second task will investigate wide bandgap (WBG)-based JFET devices and sources. The third task is an investigation into commercially available systems and components and will be performed to determine whether a standardized list of devices can be identified for reactor instrumentation application. If the devices are feasible, then this list will provide direction to designers and equipment suppliers for selection of components to meet specific reactor requirements.

42 ENGINEERING↗

NASA NTRS1978

Preamplifier Noise in VLF Receivers

Noise specifications for junction field-effect transistors are presented in different ways depending on the particular semiconductor manufacturer. Arithmetic involved in converting these specifications to equivalent RMS noise in microvolts developed at the preamplifier input terminal is reviewed. These methods were useful for estimating the noise performance of high input impedance preamplifiers used with E-field antennas operating in the range of 1 KHz to 10 MHz. Both the JFET MPF-102 transistor and the COS/MOS CA3600 transistor array provided amplification for VLF receivers where the internally generated noise was well below the atmospheric noise level. The CA3600 transistor array provided better performance because of the more symmetrical complementary MOS transistor transfer characteristics than a single N-type biased JFET transistor. The CMOS amplifier resulted in self-compensating gain characteristics over a very wide temperature range from -55 to +125 C.

Burhans, R. W.↗

NASA NTRS1982

Low-Noise Band-Pass Amplifier

Circuit uses standard components to overcome common limitation of JFET amplifiers. Low-noise band-pass amplifier employs JFET and operational amplifier. High gain and band-pass characteristics are achieved with suitable choice of resistances and capacitances. Circuit should find use as low-noise amplifier, for example as first stage instrumentation systems.

Kleinberg, L.↗

NASA NTRS1986

Development of low-temperature transistor modules to improve the MSFC mid-infrared array

This report describes the low-temperature transistor modules designed for use with the MSFC mid-infrared array. The modules were developed in the Space Science Laboratory at Marshall Space Flight Center with Center Director's Discretionary Funds. The transistors (JFETs), which operate at a temperature of 77 K, are epoxied to a copper surface attached to a Teflon substrate. The module substrate insulates the JFETs from the 1.5K detector work surfaces and provides a convenient mounting structure for additional components such as solder pins. These modules have maintained their structural integrity during repeated temperature cycling, and they have to be convenient during maintenance and servicing of the infrared array.

Telesco, C. M.↗

NASA NTRS1983

Low background IR detector and detector array evaluations

A technology program has been underway at Ames since 1978 to develop and evaluate detectors and integrated detector arrays for low-background astronomical applications. The approach is to evaluate existing (less than 24 micron) array technology under low-background conditions, with the aim of adapting and optimizing existing devices. For longer wavelengths, where the technology is much less mature, development is sponsored and devices are evaluated, in both discrete and array formats, for eventual applications. The status of this program has been reported previously. We rely on industrial and university sources for the detectors. Typically, after a brief functionality check in the supplier's laboratory, we work with the device at Ames to characterize its low-background performance. In the case of promising arrays or detectors, we conduct ground-based telescope testing to face the problems associated with real applications. A list of devices tested at Ames is given. In the array category, accumulation-mode charge-injection-devices (AMCIDs) appear repeatedly; this reflects our recent experience with the 2 x 64 and 16 x 16 arrays. Results from the 1 x 16 CID and InSb CCD have been reported. The status of our tests of the discrete Ge:x detectors from Lawrence Berkeley Laboratory are described below. Tests of a 1 x 2 switched sample photoconductor array are just beginning. A 32-channel CMOS multiplexer has been tested at 10 K. Low-temperature silicon MOSFETs and germanium JFETs have also been tested, primarily at Ball Aerospace. This paper describes results to date on three elements of this program: AMCID array, discrete Ge:Ga detectors, and Ge JFET preamplifiers.

Goebel, J. H.↗

NASA NTRS1995

Monolithic Active-Pixel Infrared Sensors

Monolithic arrays of active-pixel junction field-effect (JFET) devices made from InGaAs proposed for use as imaging sensors sensitive to light in visible and short-wavelength infrared parts of electromagnetic spectrum. Each pixel of such array comprises photodetector monolithically integrated with JFET output-amplifier circuit of source-follower type - structure similar to charge-coupled device (CCD). Sizes of instruments reduced because large cooling systems not needed.

Fossum, Eric R.↗

NASA NTRS1996

AlGaN Channel Transistors for Power Management and Distribution

Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.

ENERGY MANAGEMENT↗

NASA NTRS2002

SHARC II: A Caltech Submillimeter Observatory Facility Camera with 384 Pixels

SHARC II is a background-limited 350 micron and 450 micron facility camera for the Caltech Submillimeter Observatory undergoing commissioning in 2002. The key component of SHARC II is a 12 x 32 array of doped silicon 'pop-up' bolometers developed at NASA/Goddard. Each 1 mm x 1 mm pixel is coated with a 400 Omega/square bismuth film and located lambda/4 above a reflective backshort to achieve greater than 75% absorption efficiency. The pixels cover the focal plane with greater than 90% filling factor. At 350 microns, the SHARC II pixels are separated by 0.65 lambda/D. In contrast to the silicon bolometers in the predecessor of SHARC II, each doped thermistor occupies nearly the full area of the pixel, which lowers the 1/f knee of tile detector noise to less than 0.03 Hz, under load, at tile bath temperature of 0.36 K. The bolometers are AC-biased and read in 'total power' mode to take advantage of the improved stability. Each bolometer is biased through a custom approx. 130 MOmega CrSi load resistor at 7 K and read with a commercial JFET at 120 K. The JFETs and load resistors are integrated with the detectors into a single assembly to minimize microphonic noise. Electrical connection across the 0.36 K to 4 K and 4 K to 120 K temperature interfaces is accomplished with lithographed metal wires on dielectric substrates. In the best 25% of winter nights on Mauna Kea, SHARC II is expected to have an NEFD at 350 micron of 1 Jy Hz(sup -1/2) or better. The new camera should be at least 4 times faster at detecting known point sources and 30 times faster at mapping large areas compared to the prior instrument.

Dowell, C. Darren↗

NASA NTRS2004

Microcalorimeters with NTD and Expitaxial Germanium Thermistors for High Resolution X-Ray Spectroscopy

This is a progress report for the second year of a three year SR&T grant to continue the advancement of NTD-based microcalorimeters. We reported last year that we re-prioritized certain aspects of the statement of work and chose to emphasize issues of array development in the first year rather than wait until year two. Consequently, some of the projects scheduled for the first year were delayed to the second year and we report on those topics here. These include: a) Measurements that map out JFET , thermistor, l/f and feedback resistor noise; b) Investigations that evaluate the limits of the JFET preamplifier circuitry as it pertains to stability at the 2 eV level; The results of a) and b) have led to preliminary measurements that demonstrate 3.08 eV resolution at 6 keV. c) Calculations that can predict the current performance.

Silver, Eric↗

NASA NTRS2008

NASA Tech Briefs, December 2008

Topics covered include: Crew Activity Analyzer; Distributing Data to Hand-Held Devices in a Wireless Network; Reducing Surface Clutter in Cloud Profiling Radar Data; MODIS Atmospheric Data Handler; Multibeam Altimeter Navigation Update Using Faceted Shape Model; Spaceborne Hybrid-FPGA System for Processing FTIR Data; FPGA Coprocessor for Accelerated Classification of Images; SiC JFET Transistor Circuit Model for Extreme Temperature Range; TDR Using Autocorrelation and Varying-Duration Pulses; Update on Development of SiC Multi-Chip Power Modules; Radio Ranging System for Guidance of Approaching Spacecraft; Electromagnetically Clean Solar Arrays; Improved Short-Circuit Protection for Power Cells in Series; Electromagnetically Clean Solar Arrays; Logic Gates Made of N-Channel JFETs and Epitaxial Resistors; Improved Short-Circuit Protection for Power Cells in Series; Communication Limits Due to Photon-Detector Jitter; System for Removing Pollutants from Incinerator Exhaust; Sealing and External Sterilization of a Sample Container; Converting EOS Data from HDF-EOS to netCDF; HDF-EOS 2 and HDF-EOS 5 Compatibility Library; HDF-EOS Web Server; HDF-EOS 5 Validator; XML DTD and Schemas for HDF-EOS; Converting from XML to HDF-EOS; Simulating Attitudes and Trajectories of Multiple Spacecraft; Specialized Color Function for Display of Signed Data; Delivering Alert Messages to Members of a Work Force; Delivering Images for Mars Rover Science Planning; Oxide Fiber Cathode Materials for Rechargeable Lithium Cells; Electrocatalytic Reduction of Carbon Dioxide to Methane; Heterogeneous Superconducting Low-Noise Sensing Coils; Progress toward Making Epoxy/Carbon-Nanotube Composites; Predicting Properties of Unidirectional-Nanofiber Composites; Deployable Crew Quarters; Nonventing, Regenerable, Lightweight Heat Absorber; Miniature High-Force, Long-Stroke SMA Linear Actuators; "Bootstrap" Configuration for Multistage Pulse-Tube Coolers; Reducing Liquid Loss during Ullage Venting in Microgravity; Ka-Band Transponder for Deep-Space Radio Science; Replication of Space-Shuttle Computers in FPGAs and ASICs; Demisable Reaction-Wheel Assembly; Spatial and Temporal Low-Dimensional Models for Fluid Flow; Advanced Land Imager Assessment System; Range Imaging without Moving Parts.

Source record↗

NASA NTRS2011

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗