Results for “MOS transistor” — Page 6

NASA NTRS1982

The damage equivalence of electrons, protons, and gamma rays in MOS devices

The results of laboratory tests to determine the radiation damage effects induced on MOS devices from Co-60, electron, and proton radiation are reported. The tests are performed to establish the relationship between the Co-60 gamma rays and the level of damage to the MOS devices in regards to different damages which can be expected with the electron and particle bombardments experienced in space applications. CMOS devices were exposed to the Co-60 gamma rays, 1 MeV electrons, and 1 MeV protons while operating at 3, 10, and 15 V. The test data indicated that the Co-60 source was reliable for an initial evaluation of the electron damages up to 2 MeV charge. A correction factor was devised for transferring the Co-60 measurements to proton damages, independent of bias and transistor types, for any orbit or environment.

Brucker, G. J.↗

NASA NTRS1999

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Biegel, Bryan A.↗

NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗