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Feedback circuit controls fluctuations in speed of synchronous ac motor. Voltage proportional to phase angle is developed by phase detector, rectified, amplified, compared to threshold, and reapplied positively or negatively to motor excitation circuit. Speed control reduces wow and flutter of audio turntables and tape recorders, and enhances hunting in gyroscope motors.
A power factor type motor controller is disclosed in which the conventional power factor constant voltage command signal is replaced during a starting interval with a graduated control voltage. This continuation-impart of a pending patent application (Serial No. 199, 765: Three Phase Factor Controller) provides a means for modifying the operation of the system for a motor start-up interval of 5 to 30 second. Using a ramp generators, an initial ramp-like signal replaces a constant power factor signal supplied by a potentiometer. The ramp-like signal is applied to a 15 terminal where it is summed with an operating power factor signal from phase detectors in order to obtain a control signal for ultimately controlling SCR devices. The SCR devices are turned on at an advancing rate with time responsive to the combination signal described rather than simply a function of a ramp-like signal alone.
A discriminator aided technique for acquisition of phase lock to a suppressed carrier signal utilizes a Costas loop which is initially operated open loop and control voltage for its VCXO is derived from a phase detector that compares the VCXO to a reference frequency thus establishing coarse frequency resolution with the received signal. Then the Costas loop is closed with the low-pass filter of the channel having a bandwidth much greater (by a factor of about 10) than in the I channel so that a frequency discriminator effect results to aid carrier resolution. Finally, after carrier acquisition, the Q-channel filter of the Costas loop is switched to a bandwidth substantially equal to that of the I-channel for carrier tracking.
A circuit level analysis for residual carrier tracking of a deep space network signal by a proposed Block V receiver as conceived by the Receiver Advanced Development Team is presented. The objective is to aid the circuit designer in selection of loop parameters to achieve the required performance objectives. The topics specifically addressed are: (1) loop stability and gain requirements, (2) loop component parametric equations, and (3) phase detector technology.
The design of an integrated modem/codec unit which can receive coded and uncoded BPSK an QPSK using de facto standard coding schemes as well as 8PSK-TCM and 16PSK-TCM is examined. The design is totally compatible with today's modulation schemes and capable of processing tomorrow's TCM codes. This is accomplished in the modem by using quadrature channel carrier recovery processing and a version of the MAP phase detector algorithm. The symbol synchronization is accomplished with a derivative of an early-late gate designed to accommodate multilevel signals.
Computer simulated noise performance of the symbol synchronizer loop (SSL) in the Block 5 receiver is compared with the theoretical noise performance. Good agreement is seen at the higher loop SNR's (SNR(sub L)'s), with gradual degradation as the SNR(sub L) is decreased. For the different cases simulated, cycle slipping is observed (within the simulation time of 10(exp 4) seconds) at SNR(sub L)'s below different thresholds, ranging from 6 to 8.5 dB, comparable to that of a classical phase-locked loop. An important point, however, is that to achieve the desired loop SNR above the seemingly low threshold to avoid cycle slipping, a large data-to-loop-noise power ratio, P(sub D)/(N(sub 0)B(sub L)), is necessary (at least 13 dB larger than the desired SNR(sub L) in the optimum case and larger otherwise). This is due to the large squaring loss (greater than or equal to 13 dB) inherent in the SSL. For the special case of symbol rates approximately equaling the loop update rate, a more accurate equivalent model accounting for an extra loop update period delay (characteristic of the SSL phase detector design) is derived. This model results in a more accurate estimation of the noise-equivalent bandwidth of the loop.
Phase-shifted, laser feedback interferometry is a new diagnostic tool developed at the NASA Lewis Research Center under the Advanced Technology Development (ATD) Program directed by NASA Headquarters Microgravity Research Division. It combines the principles of phase-shifting interferometry (PSI) and laser-feedback interferometry (LFI) to produce an instrument that can quantify both optical path length changes and sample reflectivity variations. In a homogenous medium, the optical path length between two points is the product of the index of refraction and the geometric distance between the two points. LFI differs from other forms of interferometry by using the laser as both the source and the phase detector. In LFI, coherent feedback of the incident light either reflected directly from a surface or reflected after transmission through a region of interest will modulate the output intensity of the laser. The combination of PSI and LFI has produced a robust instrument, based on a low-power helium-neon (HeNe) gas laser, with a high dynamic range that can be used to measure either static or oscillatory changes of the optical path length. Small changes in optical path length are limited by the fraction of a fringe that can be measured; we can measure nonoscillatory changes with a root mean square (rms) error of the wavelength/1000 without averaging.
A hot gas turbine engine capacitive probe clearanceometer is employed to measure the clearance gap or distance between blade tips on a rotor wheel and its confining casing under operating conditions. A braze sealed tip of the probe carries a capacitor electrode which is electrically connected to an electrical inductor within the probe which is inserted into a turbine casing to position its electrode at the inner surface of the casing. Electrical power is supplied through a voltage controlled variable frequency oscillator having a tuned circuit in which the probe is a component. The oscillator signal is modulated by a change in electrical capacitance between the probe electrode and a passing blade tip surface while an automatic feedback correction circuit corrects oscillator signal drift. A change in distance between a blade tip and the probe electrode is a change in capacitance therebetween which frequency modulates the oscillator signal. The modulated oscillator signal which is then processed through a phase detector and related circuitry to provide an electrical signal is proportional to the clearance gap.
A power factor type motor controller in which the conventional power factor constant voltage command signal is replaced during a starting interval with a graduated control voltage. The present invention adds to the three-phase system of pending application Ser. No. 199,765, filed Oct. 23, 1980, means for modifying the operation of the system for a motor start-up interval of 5 to 30 seconds. The modification is that of providing via ramp generator 174 an initial ramp-like signal which replaces a constant power factor signal supplied by potentiometer 70. The ramp-like signal is applied to terminal 40 where it is summed with an operating power factor signal from phase detectors 32, 34, and 36 to thereby obtain a control signal for ultimately controlling SCR devices 12, 14, and 16 to effect a gradual turn-on of motor 10. The significant difference of the present invention over prior art is that the SCR devices are turned on at an advancing rate with time responsive to the combination signal described rather than simply a function of a ramp-like signal alone. The added signal, the operating power factor signal, enables the production of a control signal which effectively eliminates a prior problem with many motor starting circuits, which is that of accompanying motor instabilities.
An electronic signal-processing system determines the phases of input signals arriving in multiple channels, relative to the phase of a reference signal with which the input signals are known to be coherent in both phase and frequency. The system also gives an estimate of the power levels of the input signals. A prototype of the system has four input channels that handle signals at a frequency of 9.5 MHz, but the basic principles of design and operation are extensible to other signal frequencies and greater numbers of channels. The prototype system consists mostly of three parts: An analog-to-digital-converter (ADC) board, which coherently digitizes the input signals in synchronism with the reference signal and performs some simple processing; A digital signal processor (DSP) in the form of a field-programmable gate array (FPGA) board, which performs most of the phase- and power-measurement computations on the digital samples generated by the ADC board; and A carrier board, which allows a personal computer to retrieve the phase and power data. The DSP contains four independent phase-only tracking loops, each of which tracks the phase of one of the preprocessed input signals relative to that of the reference signal (see figure). The phase values computed by these loops are averaged over intervals, the length of which is chosen to obtain output from the DSP at a desired rate. In addition, a simple sum of squares is computed for each channel as an estimate of the power of the signal in that channel. The relative phases and the power level estimates computed by the DSP could be used for diverse purposes in different settings. For example, if the input signals come from different elements of a phased-array antenna, the phases could be used as indications of the direction of arrival of a received signal and/or as feedback for electronic or mechanical beam steering. The power levels could be used as feedback for automatic gain control in preprocessing of incoming signals. For another example, the system could be used to measure the phases and power levels of outputs of multiple power amplifiers to enable adjustment of the amplifiers for optimal power combining.
A truncated non-linear interferometer-based sensor system includes an input port that receives an optical beam and a non-linear amplifier that amplifies the optical beam with a pump beam and renders a probe beam and a conjugate beam. The system's local oscillators have a relationship with the respective beams. The system includes a sensor that transduces an input with the probe beam and the conjugate beam or their respective local oscillators. It includes one or more phase-sensitive detectors that detect a phase modulation between the respective local oscillators and the probe beam and the conjugate beam. Output from the phase-sensitive-detectors is based on the detected phase modulation. The phase-sensor-detectors include measurement circuitry that measure the phase signals. The measurement is the sum or difference of the phase signals in which the measured combination exhibit a quantum noise reduction in an intensity difference or a phase sum or an amplitude difference quadrature.
A vector digital signalling scheme is proposed for simultaneous adaptive data transmission and phase estimation. The use of maximum likelihood estimation methods predicts a better performance than the phase-locked loop. The phase estimate is shown to converge to the true value, so that the adaptive nature of the detector effectively achieves phase acquisition and improvement in performance. No separate synchronization interval is required and phase fluctuations can be tracked simultaneously with the transmission of information.
Mathematical model capable of performing arcsine function applicable to phase modulation receiver
An apparatus and technique are described for receiving and tracking analog or digital phase modulated signals from 0 deg to 360 deg phase shift. In order to track a signal with many phases, a detector discerns the phase modulation of the incoming signal and a phase shifter generates a negative phase shift opposite in angle to the detected phase angle. This produces a converted series sideband component barrier signal. The residual carrier signal and the converted series sideband component carrier are added together to produce a tracking carrier signal. The tracking carrier signal is multiplied with the output from a voltage controlled oscillator in the tracking loop to obtain an error signal which drives the voltage controlled oscillator and tracks the incoming signal frequency. The technique is less susceptible to carrier interference which may degrade tracking and tracking may be performed at lower signal to noise ratios and for lower input signal power levels.
Synchronous phase-lock-loop detector accepts distorted input and generates jitter-free clock. Data-detection circuitry takes advantage of this clock and employs integrate-and-dump decision circuit to provide near-theoretically ideal data decoding.
Sensitive, relatively inexpensive instrument uses phase-detection techniques to sense presence of objects. Phase-sensitive detectors, LED, photodiode with response matched to LED output, and filtering lens allow detector to operate over narrow radiation band, giving selectivity over stray light.
Phase-sensitive coherent summation of individual heterodyne detector array signals was demonstrated for the enhanced detection of spatially distorted laser Doppler returns. With the use of a 2 x 2 heterodyne detector array, the phase and amplitude of a time-varying speckle pattern was detected, and the signal-to-noise ratio of the Doppler shift estimate was shown to be improved by a factor of 2, depending on the extent of spatial coherence loss. These results are shown to agree with a first-order analysis and indicate the advantage of coherent summation for both short-range laser Doppler velocimetry and long-range atmospheric coherent lidar.
An alternative bit synchronizer proposed for shuttle was analyzed in a noise-free environment by considering the basic operation of the loop via timing diagrams and by linearizing the bit synchronizer as an equivalent, continuous, phased-lock loop (PLL). The loop is composed of a high-frequency phase-frequency detector which is capable of detecting both phase and frequency errors and is used to track the clock, and a bit transition detector which attempts to track the transitions of the data bits. It was determined that the basic approach was a good design which, with proper implementation of the accumulator, up/down counter and logic should provide accurate mid-bit sampling with symmetric bits. However, when bit asymmetry occurs, the bit synchronizer can lock up with a large timing error, yet be quasi-stable (timing will not change unless the clock and bit sequence drift). This will result in incorrectly detecting some bits.