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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6

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NASA NTRS1984

Programmable scan/read circuitry for charge coupled device imaging detectors

A circuit for scanning and outputting the induced charges in a solid state charge coupled device (CCD) image detector is disclosed in an image detection system for use in a spacecraft attitude control system. The image detection system includes timing control circuitry for selectively controlling the output of the CCD detector so that video outputs are provided only with respect to induced charges corresponding to predetermined sensing element lines of the CCD detector. The timing control circuit and the analog to digital converter are controlled by a programmed microprocessor which defines the video outputs to be converted and further controls the timing control circuit so that no video outputs are provided during the delay associated with analog to digital conversion.

Salomon, P. M.↗

NASA NTRS1989

Raster Metafile and Raster Metafile Translator

The intent is to present an effort undertaken at NASA Langley Research Center to design a generic raster image format and to develop tools for processing images prepared in this format. Both the Raster Metafile (RM) format and the Raster Metafile Translator (RMT) are addressed. This document is intended to serve a varied audience including: users wishing to display and manipulate raster image data, programmers responsible for either interfacing the RM format with other raster formats or for developing new RMT device drivers, and programmers charged with installing the software on a host platform.

Taylor, Nancy L.↗

DOE OSTI2022

LC-MEMENTO: A Memory Model for Accelerated Architectures

With the advent of heterogeneous architectures, in particular, with the ubiquity of multi-GPU systems, it is becoming increasingly important to manage device memory efficiently in order to reap the benefits of the additional core count. To date, such responsibility mainly falls on the programmer where device-to-host data communication (and vice versa), if not done properly, may incur costly memory transfer operations and synchronization. The problem may be compounded by additional requirement to maintain system-wide memory consistency that may involve expensive synchronization overhead. In this paper, we present Location Consistency Memory Model for Enhanced Transfer Operations (LC-MEMENTO). This framework considers incorporating runtime techniques for multi-GPU memory management to support relaxed synchronization semantics and memory transfer operations automatically. Specifically, we implement a relaxed form of a memory consistency model based on the Location Consistency (LC) in an Asynchronous Many-Task Runtime (ARTS) and demonstrate that, this memory model enables additional optimization opportunities for the three representative applications encompassing different computational patterns (scientific computation, graphs, data streaming, etc.).

Memory Models, Accelerators, Adaptive Optimization↗

DOE OSTI2025

Two-Dimensional Silk Crystal Films as Matrix Layer for High-Performance Microelectronics

This study explores a bio-inspired approach for memristive devices by combining Keggin-type polyoxometalates (POMs)-[SiW 12 O 40 ] 4 (POM-T) and [PW 12 O 40 ] 3 (POM-P), with silk fibroin (SF) to create 2D SF–POM layers on highly ordered pyrolytic graphite (HOPG) as resistive switching layers for memristors. We propose that the ordered SF layer template 0D POMs facilitate the formation of conductive filaments, thereby enhancing the variability of the manufactured memristors. AFM analysis revealed that both SF and SF–POM layers shared similar morphologies, while SF–POM–T formed larger aggregates, likely due to the stronger acidity of POM-T, which probably caused SF to aggregate and alter its secondary structure. Scanning Kelvin probe microscopy (SKPM) revealed that POMs reduced the contact potential difference of HOPG, resulting in lower work functions. Compared to an SF device, the SF–POM–P device showed improved memristive behavior, with a larger current gap and good repeatability over multiple sweeps; whereas the SF–POM–T device did not exhibit memristor activity, likely due to acidity-induced disruption of the SF template’s order and CF formation. More importantly, SF–POM–P devices also demonstrated programmable memristive states. Finally, combining simulation-driven memristor modeling, we showcase a co-design workflow for advancing bioinspired memristors through new materials design, synthesis, and device modeling and development.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗

DOE OSTI2025

Machine learning for arbitrary single-qubit rotations on an embedded device

Here, in this study, we present a technique for using machine learning (ML) for single-qubit gate synthesis on field-programmable logic for a superconducting transmon-based quantum computer based on simulated studies. Our approach is multi-stage. We first “bootstrap” a model based on simulation with access to the full state vector for measuring gate fidelity. We next present an algorithm, named adapted randomized benchmarking (ARB), for fine-tuning the gate on hardware based on measurements of the devices. We also present techniques for deploying the model on programmable devices with care to reduce the required resources. While the techniques here are applied to a transmon-based computer, many of them are portable to other architectures.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS2010

System for energy harvesting and/or generation, storage, and delivery

A device and method for harvesting, generating, storing, and delivering energy to a load, particularly for remote or inaccessible applications. The device preferably comprises one or more energy sources, at least one supercapacitor, at least one rechargeable battery, and a controller. The charging of the energy storage devices and the delivery of power to the load is preferably dynamically varied to maximize efficiency. A low power consumption charge pump circuit is preferably employed to collect power from low power energy sources while also enabling the delivery of higher voltage power to the load. The charging voltage is preferably programmable, enabling one device to be used for a wide range of specific applications.

Trainor, John T.↗

NASA NTRS2011

System for energy harvesting and/or generation, storage, and delivery

Trainor, John T.↗

DOE OSTI2024

Ultrafast jet classification at the HL-LHC

Abstract Three machine learning models are used to perform jet origin classification. These models are optimized for deployment on a field-programmable gate array device. In this context, we demonstrate how latency and resource consumption scale with the input size and choice of algorithm. Moreover, the models proposed here are designed to work on the type of data and under the foreseen conditions at the CERN large hadron collider during its high-luminosity phase. Through quantization-aware training and efficient synthetization for a specific field programmable gate array, we show that O ( 100 ) ns inference of complex architectures such as Deep Sets and Interaction Networks is feasible at a relatively low computational resource cost.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS2015

Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

Application Specific Integrated Circuit (ASIC)↗

DOE OSTI2024

AEcroscopy: A Software–Hardware Framework Empowering Microscopy Toward Automated and Autonomous Experimentation

Microscopy has been pivotal in improving the understanding of structure-function relationships at the nanoscale and is by now ubiquitous in most characterization labs. However, traditional microscopy operations are still limited largely by a human-centric click-and-go paradigm utilizing vendor-provided software, which limits the scope, utility, efficiency, effectiveness, and at times reproducibility of microscopy experiments. Here, in this work, a coupled software–hardware platform is developed that consists of a software package termed AEcroscopy (short for Automated Experiments in Microscopy), along with a field-programmable-gate-array device with LabView-built customized acquisition scripts, which overcome these limitations and provide the necessary abstractions toward full automation of microscopy platforms. The platform works across multiple vendor devices on scanning probe microscopes and electron microscopes. It enables customized scan trajectories, processing functions that can be triggered locally or remotely on processing servers, user-defined excitation waveforms, standardization of data models, and completely seamless operation through simple Python commands to enable a plethora of microscopy experiments to be performed in a reproducible, automated manner. This platform can be readily coupled with existing machine-learning libraries and simulations, to provide automated decision-making and active theory-experiment optimization to turn microscopes from characterization tools to instruments capable of autonomous model refinement and physics discovery.

47 OTHER INSTRUMENTATION↗

DOE OSTI2022

Low-power anisotropic molecular electronic memristors

A molecular electronic memristor, programmable resistive memory device, promises to revolutionize next-generation flexible data storage units, offering fast, dense and ultralow power solutions. Here we report anisotropic resistive switching in molecular κ-(BEDT-TTF) 2 Cu[N(CN) 2 ]Cl memristors, consisting of alternatively segregated bis(ethylenedithio)tetrathiafulvalene (BEDT-TTF) and Cu[N(CN) 2 ]Cl layers. Electron resistance switching behavior controlled by charge tunneling in molecular memristors show a low set voltage of 0.5 V (10 V/cm) with the ON/OFF ratio of 2.3×10 3 along a-axis and a high-level endurance of 1.25×10 4 cycles along all axes. Finally, the findings of such molecular electronic crystals promise for low-power data storage memristors.

36 MATERIALS SCIENCE↗

NASA NTRS1974

Programmable physiological infusion

A programmable physiological infusion device and method are provided wherein a program source, such as a paper tape, is used to actuate an infusion pump in accordance with a desired program. The system is particularly applicable for dispensing calcium in a variety of waveforms.

Howard, W. H.↗

NASA NTRS1989

Program For A Pushbutton Display

Programmable Display Pushbutton (PDP) is pushbutton device available from Micro Switch having programmable 16X35 matrix of light-emitting diodes on pushbutton surface. Any desired legends display on PDP's, producing user-friendly applications reducing need for dedicated manual controls. Interacts with operator, calls for correct response before transmitting next message. Both simple manual control and sophisticated programmable link between operator and host system. Programmable Display Pushbutton Legend Editor (PDPE) computer program used to create light-emitting-diode (LED) displays for pushbuttons. Written in FORTRAN.

Busquets, Anthony M.↗

NASA NTRS1988

VLSI high speed packet processor

The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a packet processor card utilizing semicustom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multichannel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the packet processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semicustom VLSI logic.

Grebowsky, Gerald J.↗

NASA NTRS1990

Porous-Floating-Gate Field-Effect Transistor

Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.

Thakoor, Anilkumar P.↗

NASA NTRS1991

A Code Phase Division Multiple Access (CPDMA) technique for VSAT satellite communications

A reference concept and implementation relevant to the application of Code Phase Division Multiple Access (CPDMA) to a high capacity satellite communication system providing 16 Kbps single hop channels between Very Small Aperture Terminals (VSAT's) is described. The description includes a potential implementation of an onboard CPDMA bulk demodulator/converter utilizing programmable charge coupled device (CCD) technology projected to be available in the early 1990's. A high level description of the system architecture and operations, identification of key functional and performance requirements of the system elements, and analysis results of end-to-end system performance relative to key figures of merit such as spectral efficiency are also provided.

Bruno, R.↗

NASA NTRS1993

Low-cost TDRSS communications for NASA's long duration balloon project

A new transponder and RF ground support equipment for the NASA Tracking and Data Relay Satellite System (TDRSS) intended to support long duration scientific balloon flights in Antarctica are described. The new balloon class transponder features a highly integrated spread spectrum receiver design based on programmable charge coupled device (CCD) correlators and digital signal processing chips. The correlator chip is a Lincoln Labs 4ABC with four CCD channels. The balloon transponder is capable of reporting an estimate of its input bit error rate using digital signal processing. The TDRSS user RF test set is based on a set of RF ground support equipment capable of providing both the RF communications and direct control and monitoring necessary for transponder testing and a two-way RF link for preflight testing.

Israel, David J.↗