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DOE OSTI2020

Investigation of Dynamic Temperature-Sensitive Electrical Parameters for Medium-Voltage Low-Current Silicon Carbide and Silicon Devices

This paper presents five dynamic temperature-sensitive electrical parameters (TSEPs) for the medium-voltage silicon carbide (SiC) and silicon (Si) devices. The theoretical temperature dependence of these parameters is analyzed. A test platform that enables to implement the temperature relevant dynamic characterization is developed. The tested TSEPs are summarized in terms of their relationship with junction temperature, drain/collector current, DC voltage, and external gate resistance. The comparison between the 3 kV 12 A Si IGBT and 3.3 kV 5 A SiC MOSFET with the identical TO-263 package is conducted. The results verify that the turn-off drain-source voltage switching rate achieves better thermal sensitivity for medium-voltage low-current SiC MOSFETs compared with Si IGBTs. Both the turn-on and turn-off delay time exhibit better thermal linearity for the two devices. The turn-off delay time further achieves five times better thermal sensitivity than the turn-on delay time for investigated medium-voltage SiC MOSFETs.

Ni, Ze↗

DOE OSTI2026

Tandem Photovoltaics Core Program Final Technical Report

The Tandem Photovoltaics Core Program was a multi-year initiative aimed at advancing hybrid tandem solar cell technologies to enhance solar module efficiency beyond the limits of single junction devices. This project focused on the development, testing, and scaling of prototype photovoltaic devices, with the goal of achieving commercial relevance and driving industry adoption. The work was divided into three tasks: 1) Comparative Analysis of Tandem Technologies: This task focused on quantifying energy yield under real-world conditions and assessing economic viability of tandems relative to silicon-based modules. The project's modeling framework incorporated performance data, cost of materials, and manufacturing process impacts to optimize tandem designs 2) Tandem Integration and Prototyping: In this task, we developed innovative tandem designs by combining metal halide perovskite (MHP) top cells and silicon (Si) bottom cells. The project focuses on both mechanical integration and direct deposition techniques to enable compatibility with commercially relevant Si technologies, such as passivated contact or PERC cells. 3) Scale-up and Reliability: This task addressed the challenges of large-area fabrication by developing scalable deposition methods and robust interconnection schemes for tandems. The project looked at different accelerated testing such as thermal cycling, damp heat exposure, and potential induced degradation, to ensure long-term stability of devices in field conditions. Tandem solar cells can greatly increase module efficiency beyond conventional single junction (SJ) devices, which are approaching their theoretical limit. There are many ways to fabricate a tandem cell or module in terms of materials used, configuration, and terminal connection. This SETO core project focused critical factors in enabling tandems to enter the market, including hardware integration, technoeconomic analysis (TEA), and energy yield analysis. We focused on MHP/Si hybrid tandem solar cells and modules as a model system for their versatility in module design comparisons, providing valuable insights for other tandem options. While champion cells with areas <1cm2 are regularly demonstrated by groups around the world, it is significantly more challenging to translate these advances into modules, and fewer institutions and companies are working at the module level. This project addressed questions about module fabrication, testing, and reliability that are hard to answer without actually fabricating prototypes. We also performed analysis and road-mapping activities to understand the potential for a wider variety of tandems, including all-perovskite tandems fabricated in collaboration with the Perovskite PV core program. Detailed technical results from this project are described for each task in Section 7.

14 SOLAR ENERGY↗

DOE OSTI2020

Enabling Ultrathin III-V Solar Cells Using Dual Photonic Crystals

III-V materials provide the highest efficiencies, but the higher cost of these materials compared to other alternatives such as silicon has limited their applications. One way of reducing the costs is by minimizing the amount of material needed. In this work, using optical simulations we test light trapping layers in the front and in the back of a GaAs single junction solar cell. By using these layers, we predict that we can obtain near optically thick GaAs single junctions with only 300 nm active material, with maximum calculated J sc of 28.7 mA/cm 2 under the radiative limit.

14 SOLAR ENERGY↗

DOE OSTI2020

Nonuniform Charge Collection in SiOx-Based Passivated-Contact Silicon Solar Cells

In this contribution, we report on the charge-collection characteristics of silicon photovoltaic devices using passivated contacts based on the c-Si/SiO x /poly-Si structure. Using electron-beam induced current (EBIC) imaging in plan-view and cross-section orientations, we find that charge collection in a device with a 1.5-nm-thick SiO x layer is fairly uniform in the p-n junction region and does not appear to be influenced by pyramidal surface texture. In contrast, a device with a 2.2-nm-thick oxide layer shows significant spatial variation in the charge-collection signal. The apexes of the pyramids exhibit reduced EBIC signal whereas the valleys between adjacent pyramids show the strongest collection. Our results indicate that charge collection in c-Si/SiO x /poly-Si structures can be influenced by both the properties of the SiO x layer and surface texture.

14 SOLAR ENERGY↗

DOE OSTI2020

Revealing the Nano-Scale Structure and Properties of Pinholes in SiOx Layers for POLO Contacts

In this contribution, we report on the charge collection characteristics of silicon photovoltaic devices with passivated contacts based on the c-Si/SiOx /poly-Si structure. Using electron-beam induced current (EBIC) imaging in plan-view and cross-section orientations, we find that charge collection in a device with a 1.5-nm-thick SiOx layer is fairly uniform in the p-n junction region and does not appear to be influenced by pyramidal surface texture. In contrast, a device with a 2.2-nm-thick oxide layer shows significant spatial variation in the charge-collection signal. The locations where we observe preferential collection of excess carriers is very sensitive to the processing conditions used to grow and breakup the SiOx passivation layer. In some cases the apexes of the pyramids exhibit reduced EBIC signal as the valleys between adjacent pyramids show the strongest collection. Other conditions yield enhanced charge collection at well defined spots on pyramid faces with no observable collection in the valleys.

EBIC↗

DOE OSTI2025

Exploring transport mechanisms in atomic precision advanced manufacturing enabled pn junctions

We investigate the different transport mechanisms that can occur in pn junction devices made using atomic precision advanced manufacturing at temperatures ranging from cryogenic to room temperature. We first elucidate the potential cause of the anomalous behavior observed in the forward-bias response of these devices in recent cryogenic temperature measurements, which deviates from the theoretical response of a silicon Esaki diode. These anomalous behaviors include current suppression at low voltages in the forward-bias response and a much lower valley voltage at cryogenic temperatures than theoretically expected for a silicon diode. To investigate the potential causes of these anomalies, we studied the effects of a few possible transport mechanisms, including band-to-band tunneling, bandgap narrowing, potential impact of non-Ohmic contacts, band quantization, impact of leakage, and inelastic trap-assisted tunneling, through semi-classical simulations. We find that a combination of two sets of band-to-band tunneling (BTBT) parameters can qualitatively approximate the shape of the tunneling current at low bias. This can arise from band quantization and realignment due to the strong potential confinement in δ-layers. We also find that the lower-than-theoretically-expected valley voltage can be attributed to modifications in the electronic band structure within the δ-layer regions, leading to a significant bandgap narrowing induced by the high density of dopants. Finally, we extend our analyses to room temperature operation and predict that trap-assisted tunneling (TAT) facilitated by phonon interactions may become significant, leading to a complex superposition of BTBT and TAT transport mechanisms in the electrical measurements.

band gap↗

DOE OSTI2021

Characterization of carrier behavior in photonically excited 6H silicon carbide exhibiting fast, high voltage, bulk transconductance properties

Abstract Unabated, worldwide trends in CO 2 production project growth to > 43-BMT per year over the next two decades. Efficient power electronics are crucial to fully realizing the CO 2 mitigating benefits of a worldwide smart grid (~ 18% reduction for the United States alone). Even state-of-the-art SiC high voltage junction devices are inefficient because of slow transition times (~ 0.5-μs) and limited switching rates at high voltage (~ 20-kHz at ≥ 15-kV) resulting from the intrinsically limited charge carrier drift speed (< 2 × 10 7 -cm-s −1 ). Slow transition times and limited switch rates waste energy through transition loss and hysteresis loss in external magnetic components. Bulk conduction devices, where carriers are generated and controlled nearly simultaneously throughout the device volume, minimize this loss. Such devices are possible using below bandgap excitation of semi-insulating (SI) SiC single crystals. We explored carrier dynamics with a 75-fs single wavelength pump/supercontinuum probe and a modified transient spectroscopy technique and also demonstrated a new class of efficient, high-speed, high-gain, bi-directional, optically-controlled transistor-like power device. At a performance level six times that of existing devices, for the first time we demonstrated prototype operation at multi-10s of kW and 20-kV, 125-kHz in a bulk conduction transistor-like device using direct photon-carrier excitation with below bandgap light.

36 MATERIALS SCIENCE↗

DOE OSTI2021

SiC and GaN Devices With Cryogenic Cooling

This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.

42 ENGINEERING↗

DOE OSTI2025

Thermal Optimization and Experimental Demonstration of a Silicon Carbide, Half-Bridge Power Module

This paper describes modeling and experimental work to design and demonstrate a silicon carbide (SiC), single-side-cooled power module. Two SiC metal-oxide-semiconductor field-effect transistors (MOSFET) were used for each switch position and packaged on a metalized ceramic substrate. Thermal modeling was first conducted to optimize the module packaging to minimize junction-to-fluid thermal resistance and device temperature variations. This procedure identified the optimal device placement and baseplate thickness to maximize thermal performance. A heat exchanger - incorporating impinging jets of water-ethylene glycol - was designed to cool the module's baseplate to minimize thermal resistance and pumping power. The heat exchanger used relatively low fluid velocities (<1.5 m/s) to minimize erosion-corrosion effects and relatively large fluid channel sizes (>=1 mm) to prevent clogging. The power module concept was fabricated, and experiments were conducted to measure its thermal performance. Direct current was used to power the module devices, and junction temperatures were measured via device temperature-sensitive parameters. The experimental results were found to be in good agreement with model predictions (within 2%) and yielded junction-to-fluid thermal resistance values as low as about 15 mm2 K/W at relatively low pumping power values. The results demonstrate the improved performance associated with jet impingement cooling and represent an improvement over existing channel-flow-type cold plates, which can enable improvements to power density and reliability.

36 MATERIALS SCIENCE↗

DOE OSTI2021

Atomistic and mesoscale simulations to determine effective diffusion coefficient of fission products in SiC

The silicon carbide (SiC) layer in tristructural isotropic (TRISO) particles serves as the barrier to prevent escape of fission products produced in the fuel kernel. Knowing the diffusion coefficient of fission products through SiC is critical to determining whether fission gas can escape from the particle. It has been observed in experiments that Ag accumulated in grain boundaries and triple junctions in SiC. It is hypothesized that grain boundary diffusion is the primary pathway by which fission products penetrate the SiC layer. In this report, the effective diffusion coefficient of the fission product Ag through the grain boundary network is calculated using a combination of atomistic and phase-field methods. The grain boundary diffusion coefficient is calculated using molecular dynamics simulations. The bulk diffusion coefficient is determined using a combination of density functional theory and nudged elastic band methods. An effective diffusion coefficient is calculated, accounting for the grain structure using a phase-field method. The effective diffusion coefficient will be incorporated into Bison and fission product release calculations are compared to available experimental data.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗

DOE OSTI2020

Graphite-Embedded High-Performance Insulated Metal Substrate for Wide-Bandgap Power Modules

Emerging wide-bandgap (WBG) semiconductor devices such as silicon carbide (SiC) metal–oxide semiconductor field-effect transistors (MOSFETs) and gallium nitride high-electron-mobility transistors can handle high power in reduced semiconductor areas better than conventional Si-based devices owing to superior material properties. With increased power loss density in a WBG-based converter and reduced die size in power modules, thermal management of power devices must be optimized for high performance. Here, we present a graphite-embedded insulated metal substrate (thermally-annealed-pyrolytic-graphite-embedded insulated metal substrate—IMSwTPG) designed for WBG power modules. Theoretical thermal performance analysis of graphite-embedded metal cores is presented, with design details for IMSwTPG with embedded graphite to replace a direct-bonded copper (DBC) substrate. The proposed IMSwTPG is compared with an aluminum nitride-based DBC substrate using finite-element thermal analysis for steady-state and transient thermal performance. The solutions’ thermal performances are compared under different coolant temperature and thermal loading conditions, and the proposed substrate's electrical performance is validated with static and dynamic characterization. Using graphite-embedded substrates, junction-to-case thermal resistance of SiC MOSFETs can be reduced up to 17%, and device current density can be increased by 10%, regardless of the thermal management strategy used to cool the substrate. Reduced transient thermal impedance of up to 40% of dies owing to increased heat capacity is validated in transient thermal simulations and experiments. The half-bridge power module's electrical performance is evaluated for on -state resistance, switching performance, and switching loss at three junction temperature conditions. The proposed substrate solution has minimal impact on conduction and switching performance of SiC MOSFETs.

42 ENGINEERING↗

DOE OSTI2023

Diffused trenches for high fill-factor Low-Gain Avalanche Diodes

Low-Gain Avalanche Diodes (LGADs) are a class of silicon detectors that have been specifically designed for the fast detection of minimum ionizing particles (mips) in High-Energy Physics experiments. While they provide timing resolution on the order of a few tens of picoseconds, they cannot achieve high spatial resolution due to the intrinsic characteristics of their structures. Thus, active R&D is on-going to develop detectors based on LGADs to improve their spatial resolution while maintaining the timing performance of the LGADs. Such devices are, for example, AC-coupled LGADs and Deep-Junction LGADs. Another device option is the Trench-Isolated LGAD (TI LGAD), where trenches etched at the periphery of the pixels isolate them while providing a high fill-factor. Here, in this paper, we present a variation of this latter approach, demonstrating its feasibility by means of 2-dimensional TCAD simulations.

47 OTHER INSTRUMENTATION↗

DOE OSTI2023

Detailed investigation of electrical and optical properties of textured n-type and roughened p-type tunnel oxide passivated contacts for screen-printed double-side passivated contact silicon solar cell application

Here, this paper presents detailed characterization and analyses of the optical, electrical, and contact properties of a 35 nm phosphorus-doped (n-type) polysilicon (poly-Si) and a 250 nm boron-doped (p-type) poly-Si deposited respectively on textured and roughed surface. These layers could be applied respectively to the front and rear sides of an n-type Si to produce back junction bifacial screen-printed double-side tunnel oxide passivated contacts (DS-TOPCon) solar cells. Optical and device modeling revealed a short circuit current density loss of 1.5 mA/cm 2 and 0.5 mA/cm 2 due to absorption in the front n-TOPCon and rear side p-TOPCon layers, respectively. The passivation and contact properties including metalized and unmetallized recombination current density (J 0 ), as well as contact resistivity, were determined as a function of contact firing temperature in the range of 700~800°C. The passivation quality of the front thin n-TOPCon was found to deteriorate with increased firing temperature while the rear thick p-TOPCon improved. The study showed that the simulated contact firing at 730°C resulted in the best unmetallized double-side TOPCon precursor, with an excellent implied open-circuit voltage of 730 mV and implied fill factor of ~86 %. However, the metalized J0 increased and contact resistivity decreased monotonically with the increase in the firing temperature. The 2D device simulations revealed that these layers can produce screen-printed DS-TOPCon cells with an efficiency of ~22.5 %. Solar cell modeling also showed that the DS-TOPCon solar cell efficiency can reach 24.1 % by decreasing the n-TOPCon thickness to 20 nm and lowering the full area metalized J 0 to ~100 mA/cm 2 .

14 SOLAR ENERGY↗

DOE OSTI2023

Platinum group metal-free (PGM-free) integrated tandem junction photoelectrochemical (PEC) water splitting devices (Final Technical Report)

This project involves using solar light, a photoabsorber, and a catalyst to split water and produce hydrogen. The Department of Energy (DOE) targets for integrated photoelectrochemical (PEC) cells emphasize cost (electrode cost < $200/m 2 ), performance (> 15% solar to hydrogen (STH) efficiency), and stability (> 6 months electrode lifetime), but most approaches skew toward one specific metric. This project exploited interfacial integration of platinum group metal-free (PGM-free) catalysts on the high performance and high value tandem solar cells to attain or exceed the DOE benchmark STH energy conversion efficiency and durability. This was investigated in two thrusts by developing two PEC devices for direct comparison: the first is a high-performance monolithic device based on state-of-the-art GaInP 2 /GaAs tandem solar cells developed at National Renewable Energy Laboratory (NREL), and the second is a high-value device based on earth-abundant wide band gap photoabsorber materials including oxynitride and hybrid organic-inorganic perovskite (HOIP) coupled with commercial narrow band gap silicon (Si). Both these devices were paired with electrocatalysts developed for this purpose at Rutgers University by adapting them to thin films on the photoabsorbers. These catalysts are based on the hydrogen evolution reaction (HER) catalysts (Ni 5 P 4 ), oxygen evolution reaction (OER) catalysts (LiCo 2 O 4 ) previously developed at Rutgers for high-efficiency electrolyzers. For using the high-performance tandem solar cell and Ni 5 P 4 catalysts, we achieved a durability of > 200 h at a STH efficiency of > 10%. For using the high-value wide band gap single junction solar cells on n + Si, we achieved 0.73 mA/cm 2 at 1.23V vs reversible hydrogen electrode (RHE) and -15.9 mA/cm 2 at 0V vs RHE using the oxynitride- and HOIP-based photoelectrodes, respectively. After comparing their photocurrent densities, we down selected the HOIP photoabsorber to couple Si for fabrication of a tandem photocathode. However, due to the COVID-19 pandemic, both the laboratories at Rutgers and NREL were locked down for three months and reopened only partially in 2020. The HOIP/Si tandem photocathode using robust nickel phosphide thin film catalysts cannot be developed within the project period, which is expected to achieve a STH efficiency of > 20%. Also, the low-cost LiCo 2 O 4 OER catalysts need to replace the benchmark IrO 2 for evaluation. Finally, techonomic analysis of full high-performance and high-value integrated PEC devices needs to be carried out for comparison in terms of cost.

08 HYDROGEN↗

DOE OSTI2026

Sapphire Substrate Trenching to Advance Superconducting High-Coherence Quantum Devices

Achieving longer coherence times in superconducting qubits is essential for advancing quantum information processing and enabling scalable quantum computing. This work presents an innovative fabrication strategy focused on sapphire trenching of the substrate of superconducting high-coherence quantum devices, developed by the SQMS Nanofabrication Taskforce in collaboration with the materials characterization team. In this talk, we present a method to efficiently and consistently trench into the sapphire substrate, without compromising the surface roughness or profile of the etched sapphire. In the literature, trenching in the substrate has been shown to decrease losses, unwanted coupling and thermal stress. Sapphire’s strong covalent bonds make it harder to etch compared to silicon, yet it is more favorable for high-coherence quantum devices due to its lower dielectric losses. This innovative technique opens new possibilities for superconducting qubit fabrication: we fabricated high coherence qubit chips on sapphire substrates with trenching, to demonstrate that it will help pushing towards higher coherence times. By integrating this work with ongoing junction process optimization, design innovation, materials characterization and exploration, we outline a clear pathway toward transmon coherence times reaching millisecond scales and beyond.

Garattoni, S. [Fermilab]↗

DOE OSTI2026

Sapphire Substrate Trenching to Advance Superconducting High-Coherence Quantum Devices

Garattoni, S. [Fermilab]↗

DOE OSTI2023

Asymmetric Electrode Work Function Customization via Top Electrode Replacement in Ferroelectric and Field–Induced Ferroelectric Hafnium Zirconium Oxide Thin Films

Non-volatile memory device structures such as ferroelectric random-access memory and ferroelectric tunnel junctions employ switchable spontaneous polarization to hold binary states. These devices can potentially benefit from the imposition of spontaneous internal biases and their resulting effect on the polarization properties of the ferroelectric (or field-induced ferroelectric/ antiferroelectric) layer. While HfO 2 -based thin films are ideal candidates for implementation into these devices due to their scalability and silicon compatibility, the phase purity of these oxides is sensitive to the selection of electrode material, preventing incorporation of asymmetric electrode layers into such structures. Within this work, electrode replacement following post-metallization anneal processing is introduced as a route to achieve ferroelectric and field-induced ferroelectric Hf x Zr 1–x O 2 (HZO) thin films with electrode-independent phase constitutions. The effects of this process and the corresponding internal biases imposed across the HZO layers due to asymmetric work functions are investigated. It is shown that internal biases vary in magnitude in accordance with prediction based on the work functions of the replaced electrode layers and affect remanent polarization magnitudes. Accordingly, electrode replacement presents a processing route that can readily produce HZO films with spontaneous internal biases and electrode- independent phase constitutions, facilitating implementation of these ferroelectrics into the next generation device structures.

36 MATERIALS SCIENCE↗

DOE OSTI2020

Packaging Development for a 1200V SiC BiDFET Switch Using Highly Thermally Conductive Organic Epoxy Laminate

A novel 1.2 kV/10A, 4H-SiC monolithic, bidirectional switch has been developed for use in cycloconverter applications to facilitate high-frequency direct AC-to-AC power conversion and enables new power converter topologies. A new packaging solution, utilizing a 100 µm flexible polyimide organic laminate substrate is developed to mitigate thermo-mechanical stress during power cycling and enable smaller form factor and lower cost. Multiphysics simulations and static tests were conducted to show performance characterization of the module and compare it against metallic substrates. A new organic laminate epoxy resin composite dielectric (ERCD) is also evaluated for superior thermal performance and shows 63% reduction in junction to case resistance compared to DBC substrates.

Silicon Carbide, Bi-directional switch, BiDFET, MO↗